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1. 发明申请

US20110222339A1 NONVOLATILE MEMORY DEVICE FOR REDUCING INTERFERENCE BETWEEN WORD LINES AND OPERATION METHOD THEREOF 失效
标题翻译：用于减少字线之间的干扰的非易失性存储器件及其操作方法
公开(公告)号：US20110222339A1
公开(公告)日：2011-09-15
申请号：US13044683
申请日：2011-03-10
申请人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
发明人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
IPC分类号： G11C16/28 , G11C16/10 , G11C16/08
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/28
摘要： Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line.
摘要翻译：提供一种非易失性存储器件及其操作方法。根据本发明构思的实施例的非易失性存储器件可以包括串选择线; 地选线; 与地面选择线相邻的虚拟字线; 与虚拟字线相邻的第一字线; 以及设置在所述串选择线和所述第一字线之间的第二字线。非易失性存储器件被配置为向虚拟字线施加电压。当编程连接到第一字线的存储单元时，低于施加到第二字线的电压的第一虚拟字线电压被施加到虚拟字线。当编程连接到第二字线的存储单元时，施加到第一字线的电压和第一虚拟字线电压之间的第二虚拟字线电压被施加到伪字线。因此，当执行编程操作时，可以通过根据选择字线改变施加到虚拟字线的电压来减少连接到与虚拟字线相邻的字线的存储单元的电荷损失。

2. 发明授权

US08488386B2 Nonvolatile memory device for reducing interference between word lines and operation method thereof 失效
标题翻译：用于减少字线之间的干扰的非易失性存储器件及其操作方法
公开(公告)号：US08488386B2
公开(公告)日：2013-07-16
申请号：US13044683
申请日：2011-03-10
申请人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
发明人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/28
摘要： Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line.
摘要翻译：提供一种非易失性存储器件及其操作方法。根据本发明构思的实施例的非易失性存储器件可以包括串选择线; 地选线; 与地面选择线相邻的虚拟字线; 与虚拟字线相邻的第一字线; 以及设置在所述串选择线和所述第一字线之间的第二字线。非易失性存储器件被配置为向虚拟字线施加电压。当编程连接到第一字线的存储单元时，低于施加到第二字线的电压的第一虚拟字线电压被施加到虚拟字线。当编程连接到第二字线的存储单元时，施加到第一字线的电压和第一虚拟字线电压之间的第二虚拟字线电压被施加到伪字线。因此，当执行编程操作时，可以通过根据选择字线改变施加到虚拟字线的电压来减少连接到与虚拟字线相邻的字线的存储单元的电荷损失。

3. 发明授权

US07589374B2 Semiconductor device and related fabrication method 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US07589374B2
公开(公告)日：2009-09-15
申请号：US11699990
申请日：2007-01-31
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11541
摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.
摘要翻译：本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构图案和有源区域由器件隔离层定义。半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

4. 发明授权

US07560768B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07560768B2
公开(公告)日：2009-07-14
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

5. 发明授权

US07494871B2 Semiconductor memory devices and methods for forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07494871B2
公开(公告)日：2009-02-24
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译：半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。绝缘层覆盖选择晶体管和单元晶体管。位线在绝缘层中并且电连接到相应的选择晶体管。沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

6. 发明申请

US20090035906A1 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US20090035906A1
公开(公告)日：2009-02-05
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

7. 发明授权

US07898039B2 Non-volatile memory devices including double diffused junction regions 有权
标题翻译：包括双扩散连接区域的非易失性存储器件
公开(公告)号：US07898039B2
公开(公告)日：2011-03-01
申请号：US11675372
申请日：2007-02-15
申请人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L21/70 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译：非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度与其紧邻的多个存储单元门。还讨论了相关的制造方法。

8. 发明申请

US20070111441A1 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070111441A1
公开(公告)日：2007-05-17
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

9. 发明申请

US20070090445A1 Non-Volatile Memory Devices with Wraparound-Shaped Floating Gate Electrodes and Methods of Forming Same 失效
标题翻译：具有外置式浮动电极的非易失性存储器件及其形成方法
公开(公告)号：US20070090445A1
公开(公告)日：2007-04-26
申请号：US11464324
申请日：2006-08-14
申请人： Woon Lee , Jeong-Hyuk Choi , Jai-Hyuk Song
发明人： Woon Lee , Jeong-Hyuk Choi , Jai-Hyuk Song
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521
摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.
摘要翻译：非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

10. 发明授权

US6156605A Method of fabricating DRAM device 有权
标题翻译：制造DRAM器件的方法
公开(公告)号：US6156605A
公开(公告)日：2000-12-05
申请号：US370936
申请日：1999-08-09
申请人： Jai-Hyuk Song
发明人： Jai-Hyuk Song
IPC分类号： H01L21/8234 , H01L27/108 , H01L21/8242
CPC分类号： H01L21/823493 , H01L21/823456 , H01L27/10897
摘要： A DRAM device having a triple well structure and a manufacturing method of the device are disclosed. The DRAM device includes first and second well regions of a first conductivity type formed in a semiconductor substrate of the first conductivity type. The first and second well regions are spaced apart from each other. The DRAM device also includes a third well region of a second conductivity type formed in the semiconductor substrate to encapsulate one of the first and second well regions for electrically isolating the encapsulated region from the semiconductor substrate. At least one first MOS transistor and at least one memory cell are formed in one of the first and second well regions. At least one second MOS transistor is formed in the other of the first and second well regions. In the present invention, one of the first and second MOS transistors has a gate length less than the gate length of the other.
摘要翻译：公开了具有三重阱结构的DRAM器件和该器件的制造方法。 DRAM器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱区和第二阱区。第一和第二阱区彼此间隔开。 DRAM器件还包括形成在半导体衬底中的第二导电类型的第三阱区，以封装第一和第二阱区中的一个，用于将封装区域与半导体衬底电隔离。至少一个第一MOS晶体管和至少一个存储单元形成在第一和第二阱区域之一中。在第一和第二阱区域中的另一个中形成至少一个第二MOS晶体管。在本发明中，第一和第二MOS晶体管之一的栅极长度小于另一个的栅极长度。

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