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1. 发明授权

US07560768B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07560768B2
公开(公告)日：2009-07-14
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

2. 发明授权

US07678650B2 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07678650B2
公开(公告)日：2010-03-16
申请号：US12453721
申请日：2009-05-20
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L21/8247
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：示例性实施例提供了一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

3. 发明申请

US20090258473A1 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090258473A1
公开(公告)日：2009-10-15
申请号：US12453721
申请日：2009-05-20
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L21/762
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：示例性实施例提供了一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

4. 发明申请

US20070111441A1 Nonvolatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070111441A1
公开(公告)日：2007-05-17
申请号：US11594808
申请日：2006-11-09
申请人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
发明人： Cha-Won Koh , Byung-Hong Chung , Sang-Gyun Woo , Jeong-Lim Nam , Seok-Hwan Oh , Jai-Hyuk Song , Hyun Park , Yool Kang
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件的浮置栅极可以沿着沿着控制栅电极延伸的方向截取十字形截面。浮置栅极可以具有沿着垂直于控制栅电极的有源区延伸的方向的T形截面。浮栅电极可以包括顺序地设置在栅绝缘层上的下栅极图案，中栅极图案和上栅极图案，其中中间栅极图案的宽度大于下栅极图案和上栅极图案。中间栅极图案和上部栅极图案之间的边界可以具有圆角。

5. 发明授权

US07829437B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07829437B2
公开(公告)日：2010-11-09
申请号：US12214019
申请日：2008-06-16
申请人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
发明人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
IPC分类号： H01L21/30
CPC分类号： H01L27/11568 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551
摘要： In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.
摘要翻译：在制造半导体器件的方法中，提供分别包括多个存储单元和选择晶体管的第一衬底和第二衬底。分别在第一基板和第二基板上形成第一绝缘层和第二绝缘中间层，以覆盖存储单元和选择晶体管。部分地去除第二基板的下表面以减小第二基板的厚度。第二基板的下表面附接到第一绝缘中间层。插塞通过第二绝缘中间层，第二基板和第一绝缘夹层形成，以将第一基板和第二基板中的选择晶体管电连接到插头。因此，在热处理过程中，第一衬底中的杂质离子将不会扩散。

6. 发明申请

US20090004826A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090004826A1
公开(公告)日：2009-01-01
申请号：US12214019
申请日：2008-06-16
申请人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
发明人： Young-Hoo Kim , Hyun Park , Byung-Hong Chung , Jeong-Lim Nam
IPC分类号： H01L21/20
CPC分类号： H01L27/11568 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551
摘要： In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.
摘要翻译：在制造半导体器件的方法中，提供分别包括多个存储单元和选择晶体管的第一衬底和第二衬底。分别在第一基板和第二基板上形成第一绝缘层和第二绝缘中间层，以覆盖存储单元和选择晶体管。部分地去除第二基板的下表面以减小第二基板的厚度。第二基板的下表面附接到第一绝缘中间层。插塞通过第二绝缘中间层，第二基板和第一绝缘夹层形成，以将第一基板和第二基板中的选择晶体管电连接到插头。因此，在热处理过程中，第一衬底中的杂质离子将不会扩散。

7. 发明授权

US07745325B2 Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device 有权
标题翻译：半导体器件的布线结构，布线结构的形成方法，包括布线结构的非易失性存储器件以及非易失性存储器件的制造方法
公开(公告)号：US07745325B2
公开(公告)日：2010-06-29
申请号：US11798715
申请日：2007-05-16
申请人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
发明人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
IPC分类号： H01L21/00
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76895 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
摘要翻译：半导体器件的布线结构可以包括在衬底上的绝缘中间层，所述绝缘中间层具有具有第一宽度的线性第一沟槽和具有第二宽度的线性第二沟槽，所述线性第二沟槽与线性第一沟槽，第一宽度宽于第二宽度，以及在线性第一和第二沟槽中的导电层图案。

8. 发明申请

US20080017889A1 Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device 有权
标题翻译：半导体器件的布线结构，布线结构的形成方法，包括布线结构的非易失性存储器件以及非易失性存储器件的制造方法
公开(公告)号：US20080017889A1
公开(公告)日：2008-01-24
申请号：US11798715
申请日：2007-05-16
申请人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
发明人： Young-Ho Koh , Byung-Hong Chung , Won-Jin Kim , Hyun Park , Ji-Young Min
IPC分类号： H01L23/52 , H01L21/44 , H01L29/739 , H01L21/82 , H01L27/10
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76895 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.
摘要翻译：半导体器件的布线结构可以包括在衬底上的绝缘中间层，所述绝缘中间层具有具有第一宽度的线性第一沟槽和具有第二宽度的线性第二沟槽，所述线性第二沟槽与线性第一沟槽，第一宽度宽于第二宽度，以及在线性第一和第二沟槽中的导电层图案。

9. 发明授权

US08174336B2 Ultra-wideband balun and application module thereof 有权
标题翻译：超宽带平衡 - 不平衡变压器及其应用模块
公开(公告)号：US08174336B2
公开(公告)日：2012-05-08
申请号：US12444473
申请日：2008-03-18
申请人： Young Gon Kim , Hyun Park
发明人： Young Gon Kim , Hyun Park
IPC分类号： H03H7/42 , H03H7/38
CPC分类号： H01P5/10
摘要： A first transmission line is formed on a first surface of a substrate. A first end of the first transmission line is connected to a transmission line of an unbalanced line. A second end is connected to a first transmission line of a balanced line. A second transmission line extends from a first end of the unbalanced line, alongside the first transmission line and spaced therefrom, and is connected to a second of the transmission lines of the balanced line. A ground plane is formed on a second surface of the substrate, extends from a first end of the balanced line, and is formed along the second transmission line to which the ground plane is connected through one or more vias. A width of a portion of the ground plane adjacent to the unbalanced line is greater than a portion thereof adjacent to the balanced line.
摘要翻译：第一传输线形成在基板的第一表面上。第一传输线的第一端连接到不平衡线的传输线。第二端连接到平衡线的第一传输线。第二传输线从不平衡线的第一端沿着第一传输线延伸并与之隔开，并且连接到平衡线的第二传输线。接地平面形成在基板的第二表面上，从平衡线的第一端延伸，并且沿着通过一个或多个通孔连接到接地平面的第二传输线形成。与不平衡线相邻的接地面的一部分的宽度大于与平衡线相邻的部分的宽度。

10. 外观设计

USD641036S1 Spring type reverberator 有权
标题翻译：弹簧式混响器
公开(公告)号：USD641036S1
公开(公告)日：2011-07-05
申请号：US29301334
申请日：2008-02-22
申请人： Jong Hwan Park , Hyun Park
设计人： Jong Hwan Park , Hyun Park

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