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1. 发明授权

US5889701A Method and apparatus for selecting optimum levels for in-system programmable charge pumps 失效
标题翻译：用于选择系统内可编程电荷泵的最佳电平的方法和装置
公开(公告)号：US5889701A
公开(公告)日：1999-03-30
申请号：US99160
申请日：1998-06-18
申请人： Sunae Kang , Rafael G. San Luis, Jr. , Derek R. Curd , Ronald J. Mack
发明人： Sunae Kang , Rafael G. San Luis, Jr. , Derek R. Curd , Ronald J. Mack
IPC分类号： G06F11/00 , G11C16/30 , G11C29/44 , G11C29/50 , G11C16/04
CPC分类号： G06F11/006 , G11C16/30 , G11C29/44 , G11C29/50
摘要： A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.
摘要翻译：一个新颖的测试程序用于确定CPLD中闪存阵列的最佳可编程电荷泵电平。根据本发明的方法，自动化测试仪通过电荷泵代码的所有组合进行步骤，并尝试以每个电压组合组合闪速存储器。对于每个组合，测试结果（通过或失败）被记录并存储到地图或数组中。通过泵代码窗口的中心作为起始参考点。下一步是验证与起始参考点对应的泵代码组合相关的实际电压电平。将参考泵代码装载到器件中，并测量相应的闪存单元电压电平。如果测量的电压电平不在优选范围内，则测试仪将通过调节泵代码自动调整到优选范围。

2. 发明授权

US5689516A Reset circuit for a programmable logic device 失效
标题翻译：可编程逻辑器件的复位电路
公开(公告)号：US5689516A
公开(公告)日：1997-11-18
申请号：US670916
申请日：1996-06-26
申请人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
发明人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00
CPC分类号： G01R31/318516 , G01R31/318558 , G06F11/2215
摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.
摘要翻译：可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

3. 发明授权

US6124724A Method of increasing AC testing accuracy through linear extrapolation 失效
标题翻译：通过线性外推提高交流测试精度的方法
公开(公告)号：US6124724A
公开(公告)日：2000-09-26
申请号：US85983
申请日：1998-05-27
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G01R31/319 , G01R31/26
CPC分类号： G01R31/3191
摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.
摘要翻译：提供了一种提高AC参数测试精度的方法和系统。本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。建立所需的测试点（给定时间的期望输出电压）。使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。如果所需的测试点落在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。然后在相应的包围选通时间测试一个或多个器件的计算电压。

4. 发明授权

US06552526B1 Method of increasing AC testing accuracy through linear interpolation 有权
标题翻译：通过线性插补提高交流测试精度的方法
公开(公告)号：US06552526B1
公开(公告)日：2003-04-22
申请号：US09578793
申请日：2000-05-23
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G01R1900
CPC分类号： G01R31/3191
摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.
摘要翻译：提供了一种提高AC参数测试精度的方法和系统。本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。建立所需的测试点（给定时间的期望输出电压）。使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。如果所需的测试点落在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。然后在相应的包围选通时间测试一个或多个设备的计算电压。

5. 发明授权

US06175246B1 Method of increasing AC testing accuracy through linear extrapolation 有权
标题翻译：通过线性外推提高交流测试精度的方法
公开(公告)号：US06175246B1
公开(公告)日：2001-01-16
申请号：US09577193
申请日：2000-05-23
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G01R3126
CPC分类号： G01R31/3191
摘要： A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.
摘要翻译：提供了一种提高AC参数测试精度的方法和系统。本发明提供一种在集成电路测试装置中精确估计信号传播延迟时间的方法，其中采用多个信号传播延迟时间测量，并通过线性内插所测量的延迟来估计额外的延迟时间。建立所需的测试点（给定时间的期望输出电压）。使用样品装置，通过所需的测试点，在一段时间与电压曲线上建立斜率。如果所需的测试点在测试仪的选通时间之间，则使用线性外推来计算在两个包围选通时间必须测试的电压，以保证在期望的测试点所需的性能。然后在相应的包围选通时间测试一个或多个器件的计算电压。

6. 发明授权

US5360747A Method of reducing dice testing with on-chip identification 失效
标题翻译：通过片上识别来减少骰子测试的方法
公开(公告)号：US5360747A
公开(公告)日：1994-11-01
申请号：US74897
申请日：1993-06-10
申请人： Sheldon O. Larson , Ronald J. Mack
发明人： Sheldon O. Larson , Ronald J. Mack
IPC分类号： G01R31/26 , G06F11/22 , H01L21/66 , H01L23/544
CPC分类号： H01L22/20 , G06F11/2273 , H01L23/544 , H01L2223/5442 , H01L2223/54466 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , Y10S148/162
摘要： A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed. Once again, the wafer is subjected to adverse conditions. During the second wafer sort, the last good die on the wafer is identified and tested. Then, the next die location indicated by the tested die is tested. These steps of indicating the next die and testing that die are repeated until the first good die is tested. The present invention significantly reduces valuable test time by an amount directly related to the initial yield. Moreover, the present invention reduces wear and tear on the test equipment itself, thereby increasing the longevity of this expensive piece of equipment.
摘要翻译：提供了一种包括单个芯片的片上识别的方法。第一晶片排序包括在晶片上编程多个晶片的步骤，对每个芯片上的预定存储器单元进行编程以识别该芯片所在的晶片，并将每个芯片的位置存储在为每个晶圆。然后，对多个骰子进行预定条件。在第二晶片排序中，访问一个管芯上的预定存储器单元以确定该管芯的相关文件。然后加载关联的文件。最后，测试好的骰子。在另一个实施例中，第一晶片排序包括识别晶片上的第一个良好的管芯。在发现晶圆上的下一个好的模具之后，该模具被编程以指示进行中的良好模具的位置。重复该编程步骤，直到对晶片上的最后一个好的裸片进行编程。再次，晶片受到不利条件的影响。在第二次晶片分选期间，晶圆上的最后一个好的芯片被识别和测试。然后，测试被测试模具指示的下一个模具位置。重复这些指示下一个模具和测试该模具的步骤，直到测试第一个好的模具。本发明通过与初始产量直接相关的量显着降低有价值的测试时间。此外，本发明减少了测试设备本身的磨损，从而增加了这种昂贵的设备的寿命。

7. 发明授权

US06367041B1 Self-adaptive test program 失效
标题翻译：自适应测试程序
公开(公告)号：US06367041B1
公开(公告)日：2002-04-02
申请号：US09670992
申请日：2000-09-26
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G01R3128
CPC分类号： G01R31/01
摘要： A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.
摘要翻译：一种方法和软件设备，用于实现适应每个处理的设备批次的特性的用于集成电路设备的可动态修改的测试流程。执行足够确保特定批次的适当装置功能的经过修改的一组测试，可降低测试成本并提高测试能力。本发明的方法和系统使用包括一组可跳过测试的全套测试周期性地对预定的样本数量的设备进行采样。根据可跳过测试中的样品器件组的性能特征，在修改的测试流程中会跳过多个可跳过的测试。在使用修改的测试流程测试下一组设备后，再次对另一个样本组进行全套测试，并根据新结果调整修改的测试流程的大小和组成。

8. 发明授权

US6167545A Self-adaptive test program 失效
标题翻译：自适应测试程序
公开(公告)号：US6167545A
公开(公告)日：2000-12-26
申请号：US44585
申请日：1998-03-19
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G01R31/01 , G01R31/28
CPC分类号： G01R31/01
摘要： A method and software apparatus are provided for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. According to the method of the invention, a modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results. A test summary logs the results of regular and skippable tests, providing user access to enable system modification according to desired acceptance quality levels.
摘要翻译：提供了一种方法和软件设备，用于为适应每个被处理设备批次的特性的集成电路设备实现可动态修改的测试流程。根据本发明的方法，执行足够确保特定批次的适当装置功能的改进的一组测试，降低了测试成本并提高了测试能力。本发明的方法和系统使用包括一组可跳过测试的全套测试周期性地对预定的样本数量的设备进行采样。根据可跳过测试中的样品器件组的性能特征，在修改的测试流程中会跳过多个可跳过的测试。在使用修改的测试流程测试下一组设备后，再次对另一个样本组进行全套测试，并根据新结果调整修改的测试流程的大小和组成。测试摘要记录常规和可跳过测试的结果，提供用户访问以根据期望的接受质量水平启用系统修改。

9. 发明授权

US5923602A Method for testing floating gate cells 失效
标题翻译：浮栅单元测试方法
公开(公告)号：US5923602A
公开(公告)日：1999-07-13
申请号：US44584
申请日：1998-03-19
申请人： Mihai G. Statovici , Ronald J. Mack
发明人： Mihai G. Statovici , Ronald J. Mack
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C16/04
摘要： A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing process, at most two programming pulses are needed, the two pulses being applied with the device at minimum and maximum power supply voltage levels specified for the device. First, the cell state after an initial programming pulse with the device at a minimum power supply voltage level, tested against a minimum reference voltage level, indicates whether the cell is programming properly. If not, testing ceases immediately and the device is rejected after the first pulse. Devices passing the first reading after the first pulse are subjected to a second reading at the target (higher) reference voltage. Devices passing after the second reading are designated as passing and are subjected to the next test in the test flow. Devices failing the second reading are subjected to a second programming pulse, applied with the device at the maximum power supply voltage level, the resulting cell state providing an indication of cell programming functionality. The same pulse series can also be used to test erase functionality.
摘要翻译：描述了用于测试包括浮动栅极元件的集成电路器件单元的编程功能的方法。为了加速测试过程，最多需要两个编程脉冲，两个脉冲以设备规定的最小和最大电源电压电平施加在器件上。首先，在器件处于最小电源电压电平的初始编程脉冲之后的单元状态，针对最小参考电压电平进行测试，指示单元是否正确编程。如果没有，测试将立即停止，设备在第一个脉冲后被拒绝。在第一脉冲之后通过第一读取的器件在目标（较高）参考电压下进行第二读取。在二读后通过的装置被指定为通过，并在试验流程中进行下一次试验。二次读取失败的器件经受第二编程脉冲，以最大电源电压电平施加该器件，所得到的单元状态提供单元编程功能的指示。同样的脉冲串也可以用来测试擦除功能。

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