专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120205238A1 Electro Chemical Deposition Systems and Methods of Manufacturing Using the Same 有权
标题翻译：电化学沉积系统及其使用方法
公开(公告)号：US20120205238A1
公开(公告)日：2012-08-16
申请号：US13452298
申请日：2012-04-20
申请人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
发明人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
IPC分类号： C25D21/12 , C25D17/00
CPC分类号： H01L21/76877 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/12 , C25D21/12 , H01L21/2885
摘要： An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的电化学沉积系统。电化学沉积通过为包括阴极，阳极和多个电独立辅助电极的电极供电来执行。

2. 发明申请

US20090068771A1 Electro Chemical Deposition Systems and Methods of Manufacturing Using the Same 有权
标题翻译：电化学沉积系统及其使用方法
公开(公告)号：US20090068771A1
公开(公告)日：2009-03-12
申请号：US11852910
申请日：2007-09-10
申请人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
发明人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
IPC分类号： C25D21/12 , C25D17/00 , H01L21/66
CPC分类号： H01L21/76877 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/12 , C25D21/12 , H01L21/2885
摘要： An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的电化学沉积系统。电化学沉积通过为包括阴极，阳极和多个电独立辅助电极的电极供电来执行。

3. 发明授权

US09194036B2 Plasma vapor deposition 有权
标题翻译：等离子体气相沉积
公开(公告)号：US09194036B2
公开(公告)日：2015-11-24
申请号：US11851269
申请日：2007-09-06
申请人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
发明人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
IPC分类号： C23C14/34 , H01J37/34
CPC分类号： C23C14/3464 , C23C14/3407 , C23C14/3471 , H01J37/34 , H01J37/3414 , H01J37/3417 , H01J37/3423
摘要： A plasma vapor deposition system is described for forming a feature on a semiconductor wafer. The plasma vapor deposition comprises a primary target electrode and a plurality of secondary target electrodes. The deposition is performed by sputtering atoms off the primary and secondary target electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的等离子体气相沉积系统。等离子体气相沉积包括主要目标电极和多个次要目标电极。通过从初级和次级目标电极溅射原子来进行沉积。

4. 发明申请

US20090065349A1 Plasma Vapor Deposition 有权
标题翻译：等离子体气相沉积
公开(公告)号：US20090065349A1
公开(公告)日：2009-03-12
申请号：US11851269
申请日：2007-09-06
申请人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
发明人： Sun-Oo Kim , Moosung Chae , Bum Ki Moon
IPC分类号： C23C14/00
CPC分类号： C23C14/3464 , C23C14/3407 , C23C14/3471 , H01J37/34 , H01J37/3414 , H01J37/3417 , H01J37/3423
摘要： A plasma vapor deposition system is described for forming a feature on a semiconductor wafer. The plasma vapor deposition comprises a primary target electrode and a plurality of secondary target electrodes. The deposition is performed by sputtering atoms off the primary and secondary target electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的等离子体气相沉积系统。等离子体气相沉积包括主要目标电极和多个次要目标电极。通过从初级和次级目标电极溅射原子来进行沉积。

5. 发明授权

US08197660B2 Electro chemical deposition systems and methods of manufacturing using the same 有权
标题翻译：电化学沉积系统及使用其的制造方法
公开(公告)号：US08197660B2
公开(公告)日：2012-06-12
申请号：US11852910
申请日：2007-09-10
申请人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
发明人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
IPC分类号： C25D5/00
CPC分类号： H01L21/76877 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/12 , C25D21/12 , H01L21/2885
摘要： An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的电化学沉积系统。电化学沉积通过为包括阴极，阳极和多个电独立辅助电极的电极供电来执行。

6. 发明申请

US20080173538A1 Method and apparatus for sputtering 审中-公开
标题翻译：溅射的方法和装置
公开(公告)号：US20080173538A1
公开(公告)日：2008-07-24
申请号：US11655488
申请日：2007-01-19
申请人： Sun-Oo Kim , Bum Ki Moon , Erdom Kaltalioglu
发明人： Sun-Oo Kim , Bum Ki Moon , Erdom Kaltalioglu
IPC分类号： C23C14/34
CPC分类号： H01J37/34 , H01J37/32082 , H01J37/32706
摘要： A sputtering apparatus includes a target electrode and a bias source electrically coupled to the target electrode. A wafer chuck is spaced from the target electrode. The wafer chuck is partitioned into a plurality of zones, each zone being coupled to receive an AC signal having an amplitude that can vary by zone. At least one RF coil is positioned adjacent a space between the target electrode and the wafer chuck.
摘要翻译：溅射装置包括目标电极和与靶电极电耦合的偏压源。晶片卡盘与目标电极间隔开。晶片卡盘被划分成多个区域，每个区域被耦合以接收具有可以随区域变化的幅度的AC信号。至少一个RF线圈被定位成邻近目标电极和晶片卡盘之间的空间。

7. 发明申请

US20100203701A1 Crack Stop and Moisture Barrier 有权
标题翻译：破裂停止和防潮
公开(公告)号：US20100203701A1
公开(公告)日：2010-08-12
申请号：US12766709
申请日：2010-04-23
申请人： Sun-Oo Kim , O Seo Park
发明人： Sun-Oo Kim , O Seo Park
IPC分类号： H01L21/78 , H01L21/76
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.
摘要翻译：用于半导体器件的裂纹阻挡和湿气屏障的设计包括形成在靠近划线的集成电路的边缘处的多个离散的导电特征。离散的导电特征可以包括多个交错线，多个马蹄形线，或两者的组合。

8. 发明申请

US20100087042A1 Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein 有权
标题翻译：制造具有平面金属 - 绝缘体 - 金属和垂直电容器的三维电容结构的方法
公开(公告)号：US20100087042A1
公开(公告)日：2010-04-08
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

9. 发明申请

US20050048765A1 Sealed pores in low-k material damascene conductive structures 有权
标题翻译：低k材料镶嵌导电结构中的密封孔
公开(公告)号：US20050048765A1
公开(公告)日：2005-03-03
申请号：US10654143
申请日：2003-09-03
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L21/768 , H01L21/331 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An oxide layer is used to seal pores in porous low-dielectric constant materials, thus preventing the migration of subsequently deposited copper materials into the porous low-dielectric constant materials in damascene processes. The oxide layer is deposited over the inner surface of at least one pore along a sidewall of the patterned low-dielectric constant material. In one embodiment, the oxide layer is deposited using atomic layer deposition (ALD), and the oxide layer comprises SiO2.
摘要翻译：使用氧化物层来密封多孔低介电常数材料中的孔，从而防止随后沉积的铜材料在镶嵌工艺中迁移到多孔低介电常数材料中。氧化物层沿图案化的低介电常数材料的侧壁沉积在至少一个孔的内表面上。在一个实施例中，使用原子层沉积（ALD）沉积氧化物层，并且氧化物层包含SiO 2。

10. 发明授权

US08298730B2 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08298730B2
公开(公告)日：2012-10-30
申请号：US13072227
申请日：2011-03-25
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： G03F1/20
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式