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1. 发明申请

US20100087042A1 Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein 有权
标题翻译：制造具有平面金属 - 绝缘体 - 金属和垂直电容器的三维电容结构的方法
公开(公告)号：US20100087042A1
公开(公告)日：2010-04-08
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

2. 发明申请

US20090057826A1 Semiconductor Devices and Methods of Manufacture Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090057826A1
公开(公告)日：2009-03-05
申请号：US11849539
申请日：2007-09-04
申请人： Sun-Oo Kim , Yoon-Hae Kim
发明人： Sun-Oo Kim , Yoon-Hae Kim
IPC分类号： H01L29/00 , H01G4/00 , H01L21/02
CPC分类号： H01G4/005 , H01L23/5223 , H01L27/0203 , H01L28/87 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，电容器板包括第一螺旋桨形部分和第二螺旋桨形部分。通孔部分设置在第一螺旋桨形部分和第二螺旋桨形部分之间。

3. 发明授权

US07879681B2 Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein 有权
标题翻译：制造其中具有平面金属 - 绝缘体金属和垂直电容器的三维电容器结构的方法
公开(公告)号：US07879681B2
公开(公告)日：2011-02-01
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

4. 发明授权

US07732315B2 Methods of fabricating semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US07732315B2
公开(公告)日：2010-06-08
申请号：US11849535
申请日：2007-09-04
申请人： Sun-Oo Kim , Yoon-Hae Kim
发明人： Sun-Oo Kim , Yoon-Hae Kim
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/7682 , H01L21/76835 , H01L21/7684 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material.
摘要翻译：公开了制造半导体器件的方法及其结构。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成第一绝缘材料，以及在第一绝缘材料中形成多个第一特征和多个第二特征。去除多个第一特征，在第一绝缘材料中留下未填充图案。第一绝缘材料中的未填充图案填充有第二绝缘材料。

5. 发明申请

US20090057923A1 Methods of Fabricating Semiconductor Devices and Structures Thereof 有权
标题翻译：制造半导体器件及其结构的方法
公开(公告)号：US20090057923A1
公开(公告)日：2009-03-05
申请号：US11849535
申请日：2007-09-04
申请人： Sun-Oo Kim , Yoon-Hae Kim
发明人： Sun-Oo Kim , Yoon-Hae Kim
IPC分类号： H01L23/52 , H01L21/311 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/7682 , H01L21/76835 , H01L21/7684 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material.
摘要翻译：公开了制造半导体器件的方法及其结构。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成第一绝缘材料，以及在第一绝缘材料中形成多个第一特征和多个第二特征。去除多个第一特征，在第一绝缘材料中留下未填充图案。第一绝缘材料中的未填充图案填充有第二绝缘材料。

6. 发明申请

US20110312152A1 Methods of Fabricating Integrated Circuit Devices Using Selective Etching Techniques that Account for Etching Distance Variations 审中-公开
标题翻译：使用选择性蚀刻技术制造集成电路器件的方法，其考虑蚀刻距离变化
公开(公告)号：US20110312152A1
公开(公告)日：2011-12-22
申请号：US12816649
申请日：2010-06-16
申请人： Yoon-Hae Kim , Je-Don Kim , Young-Mook Oh
发明人： Yoon-Hae Kim , Je-Don Kim , Young-Mook Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/31116 , H01L27/0733 , H01L27/0805
摘要： Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance. A step is performed to selectively etch first and second via holes of unequal size in the interlayer insulating layer to expose the upper surface of the lower capacitor electrode and the upper surface of the upper capacitor electrode, respectively. This etching step is performed using an etching process that concurrently etches portions of the interlayer insulating layer associated with the first via hole at a faster rate than portions of the interlayer insulating layer associated with the second via hole, which is larger than the first via hole.
摘要翻译：制造集成电路器件的方法包括在衬底上形成集成电路电容器。该集成电路电容器包括下电容器电极，下电容器电极上的电容器介电区域和电容器电介质区域上的上电容器电极。上部电容器电极相对于下部电容器电极具有较小的表面积。在集成电路电容器上形成层间绝缘层。对该层间绝缘层进行研磨，使其平坦化面与上部电容电极的上表面隔开第一距离，并与下部电容电极的上表面间隔大于第一距离的第二距离。执行步骤以选择性地蚀刻层间绝缘层中不等尺寸的第一和第二通孔，以分别暴露下电容电极的上表面和上电容器电极的上表面。该蚀刻步骤使用蚀刻工艺进行，该蚀刻工艺以比第一通孔更大的与第二通孔相关的层间绝缘层的部分更快的速率同时蚀刻与第一通孔相关联的部分的层间绝缘层，。

7. 发明授权

US07884409B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884409B2
公开(公告)日：2011-02-08
申请号：US11760092
申请日：2007-06-08
申请人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
发明人： Yoon-Hae Kim , Myoung-Hwan Oh , Myung-Soo Yeo , Hea-Yean Park
IPC分类号： H01L27/108 , H01L29/94 , H01L21/02 , H01L23/52
CPC分类号： H01L28/60 , H01L21/76816
摘要： A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.
摘要翻译：一种半导体器件及其制造方法，其中插入绝缘层以将半导体器件依次配置在半导体衬底上。半导体器件包括第一导电板，第二导电板，第三导电板和第四导电板。第一第二，第三和第四导电板中的至少两个电连接并构成至少两个电容器。

8. 发明授权

US07202160B2 Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
标题翻译：形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法
公开(公告)号：US07202160B2
公开(公告)日：2007-04-10
申请号：US10899934
申请日：2004-07-27
申请人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
发明人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/3122 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.
摘要翻译：在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。

9. 发明授权

US08633520B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08633520B2
公开(公告)日：2014-01-21
申请号：US12909002
申请日：2010-10-21
申请人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
发明人： Dong-Hee Yu , Bong-Seok Suh , Yoon-Hae Kim , O Sung Kwon , Oh-Jung Kwon
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76813 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided. The semiconductor device includes: a substrate; device isolation regions formed in the substrate; an impurity region formed in a region of the substrate between every two adjacent ones of the device isolation regions; a gate electrode formed on the substrate; first and second interlayer insulating films sequentially formed on the substrate; a metal interlayer insulating film formed on the second interlayer insulating film and comprising metal wiring layers; a first contact plug electrically connecting each of the metal wiring layers and the impurity region; and a second contact plug electrically connecting each of the metal wiring layers and the gate electrode, wherein the first contact plug is formed in the first and second interlayer insulating films, and the second contact plug is formed in the second interlayer insulating film.
摘要翻译：提供半导体器件。半导体器件包括：衬底; 在衬底中形成的器件隔离区; 在每隔两个相邻的器件隔离区域之间形成在衬底的区域中的杂质区; 形成在所述基板上的栅电极; 顺序形成在基板上的第一和第二层间绝缘膜; 形成在所述第二层间绝缘膜上并且包括金属布线层的金属层间绝缘膜; 电连接每个金属布线层和杂质区的第一接触插塞; 以及第二接触插塞，其电连接每个所述金属布线层和所述栅电极，其中所述第一接触插塞形成在所述第一和第二层间绝缘膜中，并且所述第二接触插塞形成在所述第二层间绝缘膜中。

10. 发明授权

US08404580B2 Methods for fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08404580B2
公开(公告)日：2013-03-26
申请号：US13444175
申请日：2012-04-11
申请人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Yoon-Hae Kim , Doo-Sung Yun
发明人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Yoon-Hae Kim , Doo-Sung Yun
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76811 , H01L21/76877
摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.
摘要翻译：在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。通过用导电材料填充第一沟槽来形成镶嵌线。

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