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1. 发明授权

US08298730B2 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08298730B2
公开(公告)日：2012-10-30
申请号：US13072227
申请日：2011-03-25
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： G03F1/20
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

2. 发明申请

US20110171821A1 Semiconductor Devices and Methods of Manufacturing Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110171821A1
公开(公告)日：2011-07-14
申请号：US13072227
申请日：2011-03-25
申请人： O Seo Park , Sun-Oo Kim , Klaus Herold
发明人： O Seo Park , Sun-Oo Kim , Klaus Herold
IPC分类号： H01L21/4763 , G06F17/50 , G03F1/00
CPC分类号： H01L23/5226 , G03F1/00 , G03F1/36 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.
摘要翻译：公开了半导体器件，其制造方法，光刻掩模和设计光刻掩模的方法。在一个实施例中，半导体器件包括设置在第一材料层中的多个第一特征。至少一个第二特征被布置在第二材料层中，所述至少一个第二特征被布置在多个第一特征上并耦合到多个第一特征。至少一个第二特征包括设置在多个第一特征中的至少两个之间的至少一个空隙。

3. 发明授权

US07879681B2 Methods of fabricating three-dimensional capacitor structures having planar metal-insulator-metal and vertical capacitors therein 有权
标题翻译：制造其中具有平面金属 - 绝缘体金属和垂直电容器的三维电容器结构的方法
公开(公告)号：US07879681B2
公开(公告)日：2011-02-01
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

4. 发明授权

US07732315B2 Methods of fabricating semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US07732315B2
公开(公告)日：2010-06-08
申请号：US11849535
申请日：2007-09-04
申请人： Sun-Oo Kim , Yoon-Hae Kim
发明人： Sun-Oo Kim , Yoon-Hae Kim
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/7682 , H01L21/76835 , H01L21/7684 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material.
摘要翻译：公开了制造半导体器件的方法及其结构。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片上形成第一绝缘材料，以及在第一绝缘材料中形成多个第一特征和多个第二特征。去除多个第一特征，在第一绝缘材料中留下未填充图案。第一绝缘材料中的未填充图案填充有第二绝缘材料。

5. 发明申请

US20090068771A1 Electro Chemical Deposition Systems and Methods of Manufacturing Using the Same 有权
标题翻译：电化学沉积系统及其使用方法
公开(公告)号：US20090068771A1
公开(公告)日：2009-03-12
申请号：US11852910
申请日：2007-09-10
申请人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
发明人： Moosung Chae , Bum Ki Moon , Sun-Oo Kim , Danny Pak-Chum Shum
IPC分类号： C25D21/12 , C25D17/00 , H01L21/66
CPC分类号： H01L21/76877 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/12 , C25D21/12 , H01L21/2885
摘要： An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.
摘要翻译：描述了用于在半导体晶片上形成特征的电化学沉积系统。电化学沉积通过为包括阴极，阳极和多个电独立辅助电极的电极供电来执行。

6. 发明授权

US07365025B2 Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
标题翻译：使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法
公开(公告)号：US07365025B2
公开(公告)日：2008-04-29
申请号：US11348428
申请日：2006-02-06
申请人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
发明人： Kyoung-Woo Lee , Seung-Man Choi , Ja-Hum Ku , Ki-Chul Park , Sun Oo Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/76808 , H01L21/31144
摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.
摘要翻译：形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

7. 发明申请

US20100203701A1 Crack Stop and Moisture Barrier 有权
标题翻译：破裂停止和防潮
公开(公告)号：US20100203701A1
公开(公告)日：2010-08-12
申请号：US12766709
申请日：2010-04-23
申请人： Sun-Oo Kim , O Seo Park
发明人： Sun-Oo Kim , O Seo Park
IPC分类号： H01L21/78 , H01L21/76
CPC分类号： H01L23/585 , H01L23/562 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.
摘要翻译：用于半导体器件的裂纹阻挡和湿气屏障的设计包括形成在靠近划线的集成电路的边缘处的多个离散的导电特征。离散的导电特征可以包括多个交错线，多个马蹄形线，或两者的组合。

8. 发明申请

US20100087042A1 Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein 有权
标题翻译：制造具有平面金属 - 绝缘体 - 金属和垂直电容器的三维电容结构的方法
公开(公告)号：US20100087042A1
公开(公告)日：2010-04-08
申请号：US12246093
申请日：2008-10-06
申请人： Yoon-Hae Kim , Sun-Oo Kim
发明人： Yoon-Hae Kim , Sun-Oo Kim
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , H01L23/5223 , H01L27/0688 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors.
摘要翻译：形成三维电容器网络的方法可以包括在半导体衬底上形成第一水平MIM电容器，并在第一水平MIM电容器上形成第一层间绝缘层。然后在第一层间绝缘层中形成第一垂直电容器电极，并且在第一层间绝缘层上形成第二水平MIM电容器。该第二水平MIM电容器可以通过形成上电容器电极和下电容器电极而形成。上部电容器电极可以通过第一垂直电容器电极电连接到下面的第一MIM电容器的上部电容器电极。可以形成在第一层间绝缘层中的下电容器电极可以与第一和第二MIM电容器的上电极相对延伸。

9. 发明申请

US20050048765A1 Sealed pores in low-k material damascene conductive structures 有权
标题翻译：低k材料镶嵌导电结构中的密封孔
公开(公告)号：US20050048765A1
公开(公告)日：2005-03-03
申请号：US10654143
申请日：2003-09-03
申请人： Sun-Oo Kim
发明人： Sun-Oo Kim
IPC分类号： H01L21/768 , H01L21/331 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807
摘要： An oxide layer is used to seal pores in porous low-dielectric constant materials, thus preventing the migration of subsequently deposited copper materials into the porous low-dielectric constant materials in damascene processes. The oxide layer is deposited over the inner surface of at least one pore along a sidewall of the patterned low-dielectric constant material. In one embodiment, the oxide layer is deposited using atomic layer deposition (ALD), and the oxide layer comprises SiO2.
摘要翻译：使用氧化物层来密封多孔低介电常数材料中的孔，从而防止随后沉积的铜材料在镶嵌工艺中迁移到多孔低介电常数材料中。氧化物层沿图案化的低介电常数材料的侧壁沉积在至少一个孔的内表面上。在一个实施例中，使用原子层沉积（ALD）沉积氧化物层，并且氧化物层包含SiO 2。

10. 发明授权

US6087278A Method for fabricating semiconductor devices having an HDP-CVD oxide layer as a passivation layer 有权
标题翻译：制造具有HDP-CVD氧化物层作为钝化层的半导体器件的方法
公开(公告)号：US6087278A
公开(公告)日：2000-07-11
申请号：US327678
申请日：1999-06-08
申请人： Sun Oo Kim , Han Min Kim
发明人： Sun Oo Kim , Han Min Kim
IPC分类号： H01L21/31 , H01L21/316 , H01L21/768 , H01L23/532 , H07L21/00
CPC分类号： H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76829 , H01L21/76837 , H01L23/5329 , H01L2924/0002 , Y10S438/978
摘要： There is provided a method for fabricating a semiconductor device, by which passivation layers are formed with good step coverage to prevent crack or void from being occurred in high aspect ratio of metallization layers and the time for performing the processes can be decreased to enhance the productability and the yield of the device. The method is performed as follows. Over a substrate having completed metallization layers, an oxide layer is formed as a first passivation layer by high-density plasma chemical vapor deposition (HDP-CVD). On the HDP-CVD oxide layer, a nitride layer is formed as a second passivation layer by plasma enhanced chemical vapor deposition (PECVD) or HDP-CVD.
摘要翻译：提供了一种用于制造半导体器件的方法，通过该方法形成具有良好阶梯覆盖的钝化层以防止金属层的高纵横比发生裂纹或空隙，并且可以减少执行该过程的时间以提高产品性能和设备的产量。该方法如下进行。在具有完成的金属化层的衬底上，通过高密度等离子体化学气相沉积（HDP-CVD）形成氧化物层作为第一钝化层。在HDP-CVD氧化物层上，通过等离子体增强化学气相沉积（PECVD）或HDP-CVD形成氮化物层作为第二钝化层。

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