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1. 发明授权

US08790988B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
公开(公告)号：US08790988B2
公开(公告)日：2014-07-29
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

2. 发明授权

US08901663B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
标题翻译：具有器件隔离图案的凹陷部分中的无源元件的半导体器件及其制造方法
公开(公告)号：US08901663B2
公开(公告)日：2014-12-02
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82 , H01L21/28 , H01L49/02 , H01L21/8238
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

3. 发明申请

US20140099768A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20140099768A1
公开(公告)日：2014-04-10
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/28 , H01L49/02
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

4. 发明申请

US20120043614A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20120043614A1
公开(公告)日：2012-02-23
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

5. 发明授权

US08228089B2 Wafer test method and wafer test apparatus 失效
标题翻译：晶圆试验方法和晶圆试验装置
公开(公告)号：US08228089B2
公开(公告)日：2012-07-24
申请号：US12704206
申请日：2010-02-11
申请人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
发明人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
IPC分类号： G01R31/26 , G01R31/08 , H01L21/66
CPC分类号： H01L22/14
摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.
摘要翻译：本发明的概念提供了晶片测试方法和晶片测试装置。晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻电解液在预定区域内。因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

6. 发明授权

US10128336B2 Semiconductor devices and methods for manufacturing the same 有权
公开(公告)号：US10128336B2
公开(公告)日：2018-11-13
申请号：US15009119
申请日：2016-01-28
申请人： Sangjine Park , Boun Yoon , Jeongnam Han
发明人： Sangjine Park , Boun Yoon , Jeongnam Han
IPC分类号： H01L29/66 , H01L29/08 , H01L21/8234 , H01L29/78 , H01L23/535 , H01L29/16 , H01L29/165 , H01L29/45 , H01L29/417
摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

7. 发明申请

US20100200431A1 WAFER TEST METHOD AND WAFER TEST APPARATUS 失效
标题翻译： WAFER测试方法和WAFER测试设备
公开(公告)号：US20100200431A1
公开(公告)日：2010-08-12
申请号：US12704206
申请日：2010-02-11
申请人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
发明人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
IPC分类号： G01N27/26
CPC分类号： H01L22/14
摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.
摘要翻译：本发明的概念提供了晶片测试方法和晶片测试装置。晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻电解液在预定区域内。因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

8. 发明授权

US09966432B2 Semiconductor devices including an etch stop pattern and a sacrificial pattern with coplanar upper surfaces and a gate and a gap fill pattern with coplanar upper surfaces 有权
公开(公告)号：US09966432B2
公开(公告)日：2018-05-08
申请号：US15010470
申请日：2016-01-29
申请人： Sangjine Park , Boun Yoon , Jeongnam Han
发明人： Sangjine Park , Boun Yoon , Jeongnam Han
IPC分类号： H01L29/66 , H01L29/08 , H01L21/8234 , H01L29/78 , H01L23/535 , H01L29/16 , H01L29/165 , H01L29/45 , H01L29/417
CPC分类号： H01L29/0847 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L23/535 , H01L29/1608 , H01L29/165 , H01L29/41783 , H01L29/45 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

9. 发明申请

US20120086048A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120086048A1
公开(公告)日：2012-04-12
申请号：US13192939
申请日：2011-07-28
申请人： Sangjine Park , Boun Yoon , Jeongnam Han
发明人： Sangjine Park , Boun Yoon , Jeongnam Han
IPC分类号： H01L29/772
CPC分类号： H01L29/0847 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L23/535 , H01L29/1608 , H01L29/165 , H01L29/41783 , H01L29/45 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.
摘要翻译：半导体器件和制造半导体器件的方法。半导体器件包括层叠在半导体衬底上的金属栅电极，栅极绝缘层位于其间，在金属栅电极的两侧设置在半导体衬底上的间隔结构，在两侧形成在半导体衬底中的源/漏区以及包括覆盖源极/漏极区域的底部部分和从底部部分延伸以覆盖间隔物结构的侧壁的一部分的侧壁部分的蚀刻停止图案，其中侧壁部分的上表面的蚀刻停止图案位于金属栅电极的上表面下方。

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