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1. 发明授权

US06262890B1 Computer system utilizing front and backside mounted memory controller chipsets 失效
标题翻译：计算机系统利用前置和背面安装的存储器控制器芯片组
公开(公告)号：US06262890B1
公开(公告)日：2001-07-17
申请号：US09271946
申请日：1999-03-18
申请人： Sudhir Dhawan , Mark Wayne Mueller , Peter Matthew Thomsen , Lucinda Mae Walter
发明人： Sudhir Dhawan , Mark Wayne Mueller , Peter Matthew Thomsen , Lucinda Mae Walter
IPC分类号： H05K710
CPC分类号： H05K7/1431 , G06F1/183 , G06F1/20 , H05K1/181 , H05K2201/10159 , H05K2201/10545 , H05K2201/10734 , Y02P70/611
摘要： A device for solving the electrical, physical, architectural and thermal challenges associated with designing a computer system is disclosed. A memory controller chipset having two or more chips mounted on opposite sides of a system planar helps balance the thermal profile of the system and achieve the strict spacing requirements of advanced computer processors relative to the memory controller chipset. Although the chips are staggered on opposite sides of the system planar, the adjacent edges of the chips substantially align with one another to minimize their separation.
摘要翻译：公开了一种用于解决与设计计算机系统相关的电气，物理，建筑和热挑战的装置。具有安装在系统平面的相对侧上的两个或更多个芯片的存储器控制器芯片组有助于平衡系统的热分布，并实现高级计算机处理器相对于存储器控制器芯片组的严格的间隔要求。虽然芯片在系统平面的相对侧交错，但是芯片的相邻边缘基本上彼此对准以使它们的分离最小化。

2. 发明授权

US06378027B1 System upgrade and processor service 有权
标题翻译：系统升级和处理器服务
公开(公告)号：US06378027B1
公开(公告)日：2002-04-23
申请号：US09281080
申请日：1999-03-30
申请人： Richard Bealkowski , Sudhir Dhawan , Kenneth Claude Hinz , Peter Matthew Thomsen
发明人： Richard Bealkowski , Sudhir Dhawan , Kenneth Claude Hinz , Peter Matthew Thomsen
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.
摘要翻译：一种维护计算机系统的处理器阵列的方法，该方法是通过静止被选择进行维护的处理器，并从计算机的操作系统使用的处理器池中移除所选择的处理器。然后，将所选择的处理器断电，同时维持处理器阵列中其他处理器的电源和操作。所选择的处理器可能被识别为有缺陷的，或者可能被选择用于升级。处理器阵列可以包括几个处理器集群，使得停顿，去除和掉电步骤适用于一个处理集群中的所有处理器。操作系统将处理器阵列中的一个处理器分配为服务处理器，并且如果服务处理器是被选择用于维护的处理器，则OS将服务处理器功能重新分配给处理器阵列中的另一个处理器。

3. 发明授权

US06295591B1 Method of upgrading and/or servicing memory without interrupting the operation of the system 失效
标题翻译：在不中断系统操作的情况下升级和/或维修存储器的方法
公开(公告)号：US06295591B1
公开(公告)日：2001-09-25
申请号：US09281084
申请日：1999-03-30
申请人： Richard Bealkowski , Scott Douglas Clark , Sudhir Dhawan , Robert Allen Drehmel
发明人： Richard Bealkowski , Scott Douglas Clark , Sudhir Dhawan , Robert Allen Drehmel
IPC分类号： G06F1200
CPC分类号： G11C29/74
摘要： A method of providing maintenance for a memory device of a computer system without interrupting operation of the computer system, by partially mirroring a primary memory array in a secondary memory array, wherein the secondary memory array has a different amount of available memory than the primary memory array. Values are copied from the primary memory array to the permanent storage device, allowing the primary memory array to quiesce and be serviced while using the secondary memory array to operate the computer system. Thereafter, the primary memory array is brought on-line, and the mirrored values are written back from the secondary memory array to the primary memory array. The memory service program itself may be embedded in the operating system. In an illustrative embodiment, the primary memory array is located on a first removable memory card, and the secondary memory array is located on a second removable memory card. The amount of memory available in the secondary memory array may be programmable.
摘要翻译：一种通过部分地镜像辅助存储器阵列中的主存储器阵列来为计算机系统的存储器件提供维护而不中断计算机系统的操作的方法，其中辅助存储器阵列具有与主存储器不同的可用存储器量数组。值从主存储器阵列复制到永久存储设备，允许主存储器阵列静止并被服务，同时使用辅助存储器阵列来操作计算机系统。此后，主存储器阵列被联机，并且镜像值从副存储器阵列写回主存储器阵列。存储器服务程序本身可以嵌入在操作系统中。在说明性实施例中，主存储器阵列位于第一可移动存储卡上，并且辅助存储器阵列位于第二可移动存储卡上。辅助存储器阵列中可用的存储器量可以是可编程的。

4. 发明授权

US5491811A Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory 失效
标题翻译：缓存系统使用掩码位来记录通过缓存到系统内存的数据传输顺序
公开(公告)号：US5491811A
公开(公告)日：1996-02-13
申请号：US871322
申请日：1992-04-20
申请人： Ravi K. Arimilli , Sudhir Dhawan , David W. Siegel
发明人： Ravi K. Arimilli , Sudhir Dhawan , David W. Siegel
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859
摘要： Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.
摘要翻译：在与高速缓存结合操作的系统存储器的上下文中提高数据传送速率的装置和方法。在一种形式中，掩码位寄存器中的掩码位与高速缓存的字节相关联。写入高速缓存中的相应字节时，掩码位被改变。掩码位用于重新排序的操作序列，以便在写入高速缓存之后选择性地将数据从系统存储器写入高速缓存。数据传输性能得到显着改善，因为当数据传输到高速缓存中时，掩码位指示高速缓存（通常为高速缓存行）的整个单元已被写入时，可以完全消除从系统存储器到高速缓存的数据选择性写入。

5. 发明授权

US5274784A Data transfer using bus address lines 失效
标题翻译：使用总线地址线进行数据传输
公开(公告)号：US5274784A
公开(公告)日：1993-12-28
申请号：US791468
申请日：1991-11-13
申请人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
发明人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
IPC分类号： G06F13/28 , G06F13/42 , G06F13/00
CPC分类号： G06F13/28 , G06F13/4217
摘要： A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.
摘要翻译：在高速数据传输期间，计算机系统可以在总线地址线上的主子系统和从属子系统之间传送数据以及总线数据线。数据在高速传输期间通过与正常总线时钟信号分离的高速时钟信号来计时。数据以主子系统和从属子系统可以处理的最大速率传输。

6. 发明授权

US5237676A High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device 失效
标题翻译：调整数据传输速度的高速数据传输系统对连接设备的指示传输速度能力的响应
公开(公告)号：US5237676A
公开(公告)日：1993-08-17
申请号：US297773
申请日：1989-01-13
申请人： Ravi K. Arimilli , Sudhir Dhawan , George A. Lerom , James O. Nicholson , David W. Siegel
发明人： Ravi K. Arimilli , Sudhir Dhawan , George A. Lerom , James O. Nicholson , David W. Siegel
IPC分类号： G06F13/28 , G06F13/42
CPC分类号： G06F13/4217 , G06F13/28
摘要： A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

7. 发明授权

US07251185B2 Methods and apparatus for using memory 有权
标题翻译：使用记忆的方法和装置
公开(公告)号：US07251185B2
公开(公告)日：2007-07-31
申请号：US11064741
申请日：2005-02-24
申请人： John M. Borkenhagen , Sudhir Dhawan , Philip R. Hillier, III , Joseph A. Kirscht , Randolph S. Kolvick
发明人： John M. Borkenhagen , Sudhir Dhawan , Philip R. Hillier, III , Joseph A. Kirscht , Randolph S. Kolvick
IPC分类号： G11C8/00
CPC分类号： G06F11/1666 , G06F11/20 , G06F12/0607
摘要： In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种用于使用存储器的方法。该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分被替换和（2）将数据存储在总存储器中。提供了许多其他方面。

8. 发明申请

US20060187739A1 Methods and apparatus for using memory 有权
标题翻译：使用记忆的方法和装置
公开(公告)号：US20060187739A1
公开(公告)日：2006-08-24
申请号：US11064741
申请日：2005-02-24
申请人： John Borkenhagen , Sudhir Dhawan , Philip Hillier , Joseph Kirscht , Randolph Kolvick
发明人： John Borkenhagen , Sudhir Dhawan , Philip Hillier , Joseph Kirscht , Randolph Kolvick
IPC分类号： G11C8/00
CPC分类号： G06F11/1666 , G06F11/20 , G06F12/0607
摘要： In an aspect, a method is provided for using memory. The method includes the steps of (1) employing memory stacking, memory mirroring and memory interleaving in a total memory to reduce a number of memory entries that are written to an input/output (I/O) device while a portion of the total memory is replaced; and (2) storing data in the total memory. Numerous other aspects are provided.
摘要翻译：在一方面，提供了一种使用存储器的方法。该方法包括以下步骤：（1）在总存储器中采用存储器堆叠，存储器镜像和存储器交错以减少写入输入/输出（I / O）设备的存储器条目的数量，同时存储器的一部分被替换和（2）将数据存储在总存储器中。提供了许多其他方面。

9. 发明授权

US5287482A Input/output cache 失效
标题翻译：输入/输出缓存
公开(公告)号：US5287482A
公开(公告)日：1994-02-15
申请号：US912043
申请日：1992-07-09
申请人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
发明人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/084
摘要： A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.
摘要翻译：用于连接到输入/输出总线的输入/输出设备的缓存。通过输入/输出设备访问系统内存的请求通过缓存。输入/输出设备使用的虚拟内存地址将转换为系统内存中的实际地址。可以对虚拟内存进行分区，一些虚拟地址映射到连接到输入/输出总线的第二个内存。

10. 发明申请

US20090177946A1 Memory Initialization Time Reduction 有权
标题翻译：内存初始化时间缩短
公开(公告)号：US20090177946A1
公开(公告)日：2009-07-09
申请号：US11969449
申请日：2008-01-04
申请人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
发明人： Shiva R. Dasari , Sudhir Dhawan , Joseph Allen Kirscht , Jennifer L. Vargus
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
摘要翻译：一种用于改善计算机系统的存储器中的存储器初始化的方法和装置。存储器中的存储器单元包括多个等级，每个等级具有唯一的等级选择。奇偶校验发生器输出与编码秩选择是否具有偶数或奇数“1”相对应的奇偶校验位。奇偶校验位由生成ECC位的错误检查和校正（ECC）单元使用，ECC位存储在具有活动秩选择的等级中。在存储器初始化周期的第一间隔期间，并行地初始化其编码级选择中具有偶数“1”的等级。在存储器初始化期间的第二间隔期间，并行地初始化其编码秩选择中具有奇数“1”的等级。

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