专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07376038B2 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US07376038B2
公开(公告)日：2008-05-20
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

2. 发明申请

US20090262588A1 POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME 有权
标题翻译：具有水平移位边界隔离开关（LSIFF）和时钟控制数据保持方案的节电
公开(公告)号：US20090262588A1
公开(公告)日：2009-10-22
申请号：US12104580
申请日：2008-04-17
申请人： RAMAPRASATH VILANGUDIPITCHAI , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
发明人： RAMAPRASATH VILANGUDIPITCHAI , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
IPC分类号： G11C7/00
CPC分类号： H03K3/356147 , H03K3/0375
摘要： An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
摘要翻译：用于为具有数据保持的电路提供主动模式功率降低的装置包括用于锁存数据输入的主从触发器（MSFF）。耦合到MSFF的输出电平移位器（OLS）保留数据输入以响应MSFF在有功功率节省模式（APSM）中可操作以降低功率。在APSM中操作的OLS提供具有可配置电压的电平移位器输出，从而提供输出隔离。在主动模式和APSM之间的MSFF操作模式的改变与保留（RET）模式输入无关。

3. 发明授权

US07622955B2 Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme 有权
标题翻译：功率节省与电平移位边界隔离触发器（LSIFF）和时钟控制的数据保留方案
公开(公告)号：US07622955B2
公开(公告)日：2009-11-24
申请号：US12104580
申请日：2008-04-17
申请人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
发明人： Ramaprasath Vilangudipitchai , Sumanth Katte Gururajarao , Hugh T. Mair , Alice Wang , Uming U. Ko , Sushma Honnavara-Prasad
IPC分类号： H03K19/094
CPC分类号： H03K3/356147 , H03K3/0375
摘要： An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.
摘要翻译：用于为具有数据保持的电路提供主动模式功率降低的装置包括用于锁存数据输入的主从触发器（MSFF）。耦合到MSFF的输出电平移位器（OLS）保留数据输入以响应MSFF在有功功率节省模式（APSM）中可操作以降低功率。在APSM中操作的OLS提供具有可配置电压的电平移位器输出，从而提供输出隔离。在主动模式和APSM之间的MSFF操作模式的改变与保留（RET）模式输入无关。

4. 发明申请

US20070223294A1 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US20070223294A1
公开(公告)日：2007-09-27
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David Scott , Uming Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David Scott , Uming Ko , Alice Wang
IPC分类号： G11C7/00
CPC分类号： G11C8/10
摘要： A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

5. 发明授权

US07307471B2 Adaptive voltage control and body bias for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制和体偏置
公开(公告)号：US07307471B2
公开(公告)日：2007-12-11
申请号：US11213477
申请日：2005-08-26
申请人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
发明人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
IPC分类号： G05F1/565
CPC分类号： H03K19/0008 , H03K19/00384
摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.
摘要翻译：一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。该装置还包括耦合到处理模块的第二跟踪元件。第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

6. 发明申请

US20110216619A1 MEMORY POWER MANAGEMENT SYSTEMS AND METHODS 审中-公开
标题翻译：存储电源管理系统和方法
公开(公告)号：US20110216619A1
公开(公告)日：2011-09-08
申请号：US13106612
申请日：2011-05-12
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

7. 发明授权

US07961546B2 Memory power management systems and methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US07961546B2
公开(公告)日：2011-06-14
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最小存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

8. 发明申请

US20100103760A1 Memory Power Management Systems and Methods 有权
标题翻译：内存电源管理系统和方法
公开(公告)号：US20100103760A1
公开(公告)日：2010-04-29
申请号：US12258747
申请日：2008-10-27
申请人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
发明人： Hugh T. Mair , Robert L. Pitts , Alice Wang , Sumanth K. Gururjarao , Ramaprasath Vilangudipitchai , Gordon Gammie , Uming Ko
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
摘要翻译：提供了内存电源管理系统和方法。本发明的一个实施例包括存储器电源管理系统。该系统包括第一低压差（LDO）调节器，其提供从第一电源电压导出的有源工作电压，以在激活模式期间为存储器阵列供电。该系统还包括第二LDO调节器，其提供从第二电源电压导出的最低存储器保持电压，以在待机模式下为存储器阵列供电，其中第二电源电压还为至少一个外围电路供电以从其读取和/ 或写入存储器阵列。

9. 发明申请

US20090046519A1 METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE 审中-公开
标题翻译：用于配置用于改进性能的静态随机存取存储器单元的方法，装置和系统
公开(公告)号：US20090046519A1
公开(公告)日：2009-02-19
申请号：US11839464
申请日：2007-08-15
申请人： Alice Wang , David Scott , Sumanth Gururajarao , Gordon Gammie , Sudha Thiruvengadam
发明人： Alice Wang , David Scott , Sumanth Gururajarao , Gordon Gammie , Sudha Thiruvengadam
IPC分类号： G11C5/14
CPC分类号： G11C29/006 , G11C11/41 , G11C29/50
摘要： A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing.
摘要翻译：一种用于配置用于操作的静态随机存取存储器（SRAM）位单元的计算机实现的方法，自适应偏置装置和半导体晶片测试系统。在一个实施例中，该方法包括：（1）确定晶片上的SRAM位单元的性能特性，（2）将性能特性与目标进行比较，以及（3）基于所述SRAM位单元配置与SRAM位单元相关联的偏置电路比较。

10. 发明申请

US20050194592A1 Adaptive voltage control for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制
公开(公告)号：US20050194592A1
公开(公告)日：2005-09-08
申请号：US11045222
申请日：2005-01-28
申请人： Hugh Mair , Gordon Gammie , Alice Wang
发明人： Hugh Mair , Gordon Gammie , Alice Wang
IPC分类号： H01L29/04
CPC分类号： G11C5/147
摘要： A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first tracking element coupled to the processing module and producing a first value indicative of a first estimated speed associated with the circuitry, and a second tracking element coupled to the processing module and producing a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to a target value and causes a voltage output to be adjusted based on said comparison.
摘要翻译：一种用于自适应地控制提供给基本上靠近设备的电路的电压的装置，包括处理模块，耦合到处理模块的第一跟踪元件，并产生指示与电路相关联的第一估计速度的第一值，以及第二跟踪元件耦合到所述处理模块并产生指示与所述电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与目标值进行比较，并且基于所述比较使电压输出被调整。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式