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1. 发明申请

US20090046519A1 METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE 审中-公开
标题翻译：用于配置用于改进性能的静态随机存取存储器单元的方法，装置和系统
公开(公告)号：US20090046519A1
公开(公告)日：2009-02-19
申请号：US11839464
申请日：2007-08-15
申请人： Alice Wang , David Scott , Sumanth Gururajarao , Gordon Gammie , Sudha Thiruvengadam
发明人： Alice Wang , David Scott , Sumanth Gururajarao , Gordon Gammie , Sudha Thiruvengadam
IPC分类号： G11C5/14
CPC分类号： G11C29/006 , G11C11/41 , G11C29/50
摘要： A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing.
摘要翻译：一种用于配置用于操作的静态随机存取存储器（SRAM）位单元的计算机实现的方法，自适应偏置装置和半导体晶片测试系统。在一个实施例中，该方法包括：（1）确定晶片上的SRAM位单元的性能特性，（2）将性能特性与目标进行比较，以及（3）基于所述SRAM位单元配置与SRAM位单元相关联的偏置电路比较。

2. 发明申请

US20060267654A1 Ultra low area overhead retention flip-flop for power-down applications 有权
公开(公告)号：US20060267654A1
公开(公告)日：2006-11-30
申请号：US11138788
申请日：2005-05-26
申请人： Sumanth Gururajarao , Hugh Mair , David Scott , Uming Ko
发明人： Sumanth Gururajarao , Hugh Mair , David Scott , Uming Ko
IPC分类号： H03K3/356
CPC分类号： H03K3/356008 , H04W52/0283 , Y02D70/122
摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

3. 发明授权

US07327185B2 Selectable application of offset to dynamically controlled voltage supply 有权
标题翻译：可动态控制电压补偿的可选应用
公开(公告)号：US07327185B2
公开(公告)日：2008-02-05
申请号：US11264404
申请日：2005-11-01
申请人： Hugh Mair , Sumanth Gururajarao
发明人： Hugh Mair , Sumanth Gururajarao
IPC分类号： G05F1/575
CPC分类号： H03F1/0211
摘要： An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths and a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.
摘要翻译：电子系统包括多个电路路径。多个电路路径中的每个路径被耦合以从电压源接收系统电压。该系统还包括第一电路，用于提供指示多个电路路径中的至少一个路径的第一潜在能力的至少一个路径的运行速度的第一值;以及第二电路，用于提供第二值，用于指示第二电位多个电路路径中的至少一个路径。该系统还包括用于响应于第一值和第二值之间的关系来调整由电压源提供的系统电压的电路。

4. 发明授权

US07091766B2 Retention register for system-transparent state retention 有权
标题翻译：保留注册表，用于系统透明状态保留
公开(公告)号：US07091766B2
公开(公告)日：2006-08-15
申请号：US10616207
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh Mair
IPC分类号： H03K3/12 , H03K3/37 , H03K3/286 , H03K3/356
CPC分类号： H03K3/356008
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的节点（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

5. 发明授权

US07564077B2 Performance and area scalable cell architecture technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US07564077B2
公开(公告)日：2009-07-21
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

6. 发明申请

US20090097327A1 SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY 有权
标题翻译：用于从存储阵列读取数据的系统和方法
公开(公告)号：US20090097327A1
公开(公告)日：2009-04-16
申请号：US12337946
申请日：2008-12-18
申请人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
发明人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/12 , G11C11/419
摘要： One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.
摘要翻译：本发明的一个实施例包括用于从存储器阵列访问数据的列多路复用器，所述存储器阵列包括具有基于控制节点的逻辑状态的逻辑状态的输出节点和列元素，每个列元素包括第一对串联连接的开关由列选择信号和与存储在多个存储单元中的数据相关联的位线信号控制。第一对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑低电平状态。列元件每个还包括由位线信号和列选择信号的补码控制的第二对串联连接开关。第二对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑高状态。

7. 发明申请

US20080123449A1 Systems and methods for reading data from a memory array 有权
标题翻译：用于从存储器阵列读取数据的系统和方法
公开(公告)号：US20080123449A1
公开(公告)日：2008-05-29
申请号：US11594602
申请日：2006-11-08
申请人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
发明人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1048 , G11C7/12 , G11C11/419
摘要： One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.
摘要翻译：本发明的一个实施例包括用于从存储器阵列访问数据的列多路复用器，所述存储器阵列包括具有基于控制节点的逻辑状态的逻辑状态的输出节点和列元素，每个列元素包括第一对串联连接的开关由列选择信号和与存储在多个存储单元中的数据相关联的位线信号控制。第一对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑低电平状态。列元件每个还包括由位线信号和列选择信号的补码控制的第二对串联连接开关。第二对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑高状态。

8. 发明申请

US20060091385A1 Selectable application of offset to dynamically controlled voltage supply 有权
标题翻译：可动态控制电压补偿的可选应用
公开(公告)号：US20060091385A1
公开(公告)日：2006-05-04
申请号：US11264404
申请日：2005-11-01
申请人： Hugh Mair , Sumanth Gururajarao
发明人： Hugh Mair , Sumanth Gururajarao
IPC分类号： H01L29/04
CPC分类号： H03F1/0211
摘要： An electronic system. The system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a potential capability of operational speed of at least one path in the plurality of paths and a second circuit for providing a second value for indicating a potential capability of operational speed of the at least one path in the plurality of paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.
摘要翻译：电子系统。该系统包括多个电路路径。多个电路路径中的每个路径被耦合以从电压源接收系统电压。该系统还包括第一电路，用于提供指示多个路径中的至少一条路径的运行速度的潜在能力的第一值，以及用于提供第二值，用于提供第二值，用于指示所述至少一个路径的运行速度的潜在能力多个路径中的一个路径。该系统还包括用于响应于第一值和第二值之间的关系来调整由电压源提供的系统电压的电路。

9. 发明授权

US06989702B2 Retention register with normal functionality independent of retention power supply 有权
标题翻译：保持寄存器具有正常功能，独立于保持电源
公开(公告)号：US06989702B2
公开(公告)日：2006-01-24
申请号：US10613271
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C14/00
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的阳极（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

10. 发明授权

US07773431B2 Systems and methods for reading data from a memory array 有权
标题翻译：用于从存储器阵列读取数据的系统和方法
公开(公告)号：US07773431B2
公开(公告)日：2010-08-10
申请号：US12337946
申请日：2008-12-18
申请人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
发明人： Radu Avramescu , Sumanth Gururajarao , Hugh Thomas Mair
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/12 , G11C11/419
摘要： One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.
摘要翻译：本发明的一个实施例包括用于从存储器阵列访问数据的列多路复用器，所述存储器阵列包括具有基于控制节点的逻辑状态的逻辑状态的输出节点和列元素，每个列元素包括第一对串联连接的开关由列选择信号和与存储在多个存储单元中的数据相关联的位线信号控制。第一对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑低电平状态。列元件每个还包括由位线信号和列选择信号的补码控制的第二对串联连接开关。第二对开关被配置为基于位线信号的逻辑状态将控制节点设置为逻辑高状态。

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