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1. 发明授权

US08225049B2 Data storage device having self-powered semiconductor device 有权
标题翻译：具有自供电半导体器件的数据存储装置
公开(公告)号：US08225049B2
公开(公告)日：2012-07-17
申请号：US12689317
申请日：2010-01-19
申请人： Subramanya Mayya , Hee-seok Kim , Ik-Soo Kim , Min-Young Park , Hyun-Suk Kwon
发明人： Subramanya Mayya , Hee-seok Kim , Ik-Soo Kim , Min-Young Park , Hyun-Suk Kwon
IPC分类号： G06F13/16
CPC分类号： H01L27/10897 , H01L23/58 , H01L25/0657 , H01L25/16 , H01L27/10876 , H01L27/10894 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： Provided is a data storage device. The data storage device includes an interface, a buffer controller, a memory controller, a non-volatile memory, and a self-powered semiconductor device adjacent to and electrically connected to the buffer controller. The self-powered semiconductor device includes a semiconductor chip and a rechargeable micro-battery attached to the semiconductor chip. The rechargeable micro-battery includes a first current collector and a second current collector, which face each other, a first polarizing electrode in contact with the first current collector and facing the second current collector, a second polarizing electrode in contact with the second current collector and facing the first polarizing electrode, and an electrolyte layer formed between the first and second polarizing electrodes.
摘要翻译：提供了一种数据存储装置。数据存储设备包括接口，缓冲器控制器，存储器控制器，非易失性存储器以及与缓冲器控制器相邻并电连接的自供电半导体器件。自供电的半导体器件包括半导体芯片和附接到半导体芯片的可再充电微型电池。所述可再充电微电池包括彼此面对的第一集电体和第二集电体，与所述第一集电体接触并面对所述第二集电体的第一极化电极，与所述第二集电体接触的第二极化电极，并且面对第一极化电极，以及形成在第一和第二极化电极之间的电解质层。

2. 发明授权

US6025248A Methods of forming capacitor electrodes including a capacitor electrode etch 失效
标题翻译：形成电容器电极的方法包括电容器电极蚀刻
公开(公告)号：US6025248A
公开(公告)日：2000-02-15
申请号：US946334
申请日：1997-10-07
申请人： Hee-seok Kim , Jae-chul Lee , Hyun-woo Lim , Jae-hyong Lee
发明人： Hee-seok Kim , Jae-chul Lee , Hyun-woo Lim , Jae-hyong Lee
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84 , Y10S438/947 , Y10S438/964
摘要： A method of forming a capacitor includes the step of forming an electrode on an integrated circuit substrate wherein the electrode covers a first portion of the integrated circuit substrate and wherein the electrode exposes a second portion of the integrated circuit substrate. An etch masking pattern including a plurality of ions is formed on the surface of the electrode wherein the etch masking pattern exposes portions of the surface of the electrode. The exposed portions of the electrode are etched using the etch masking pattern as an etching mask so that recesses are formed in the surface of the electrode thereby increasing a surface area thereof. The etch masking pattern is removed, a dielectric layer is formed on the electrode including the recesses, and a conductive layer is formed on the dielectric layer opposite the electrode.
摘要翻译：形成电容器的方法包括在集成电路基板上形成电极的步骤，其中电极覆盖集成电路基板的第一部分，并且其中电极暴露集成电路基板的第二部分。在电极的表面上形成包括多个离子的蚀刻掩模图案，其中蚀刻掩模图案暴露电极表面的部分。使用蚀刻掩模图案作为蚀刻掩模来蚀刻电极的暴露部分，使得在电极的表面中形成凹部从而增加其表面积。去除蚀刻掩模图案，在包括凹部的电极上形成电介质层，并且在与电极相对的电介质层上形成导电层。

3. 发明申请

US20090089551A1 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system 有权
标题翻译：避免单端口多库存储系统存在冲突的装置和方法
公开(公告)号：US20090089551A1
公开(公告)日：2009-04-02
申请号：US12071910
申请日：2008-02-27
申请人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
发明人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
IPC分类号： G06F9/40 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836
摘要： Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.
摘要翻译：提供了一种避免银行冲突的方法和装置。通过将第一指令的执行定时改变为在第一指令的执行定时之前的定时，以访问指令来替换作为预测导致存储体冲突的访问指令之一的第一指令，不造成银行冲突。接下来，根据第一指令被调度为访问存储体的加载/存储单元访问存储体，并在第二指令的执行定时从存储体读出数据，然后允许加载/存储单元在第一指令的执行定时输入读数据。因此，尽管预测导致银行冲突的访问指令被分配给加载/存储单元，但是可以防止银行冲突，使得可以避免由于银行冲突的发生导致的性能下降。

4. 发明授权

US5677234A Methods of forming isolated semiconductor device active regions 失效
标题翻译：形成隔离半导体器件有源区的方法
公开(公告)号：US5677234A
公开(公告)日：1997-10-14
申请号：US665294
申请日：1996-06-18
申请人： Bon-young Koo , Byung-hong Chung , Hee-seok Kim , Yun-gi Kim
发明人： Bon-young Koo , Byung-hong Chung , Hee-seok Kim , Yun-gi Kim
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： Methods of forming semiconductor device active regions include the steps of forming a buffer layer containing a material susceptible to oxidation, such as polycrystalline or amorphous silicon, on a semiconductor substrate. To inhibit any native oxide film on the buffer layer from facilitating the formation of field oxide isolation regions having bird's beaks, the native oxide film is converted to a nitrogen containing film, such as silicon oxynitride, by nitrating the native oxide film. The silicon oxynitride film can be formed by exposing the oxide film to a nitrogen containing plasma, implanting nitrogen ions into the oxide film or annealing the oxide film in a nitrogen containing atmosphere, for example. During the nitrating step, chemically active oxygen in the native oxide film becomes bound to the nitrogen incorporated therein. A top oxidation resistant layer containing silicon nitride can then be formed on the nitrated surface of the buffer layer and used as an oxidation mask during a subsequent step of oxidizing the buffer layer to form field oxide isolation regions. By binding chemically active oxygen to nitrogen during the nitrating step, lateral oxidation under the top oxidation resistant layer is inhibited by limiting the lateral transport of chemically active oxygen. The masking properties of the top oxidation resistant layer can therefore be enhanced and utilized to form field oxide isolation regions having short or nonexistent bird beak's.
摘要翻译：形成半导体器件有源区的方法包括在半导体衬底上形成含有易于氧化的材料（例如多晶或非晶硅）的缓冲层的步骤。为了抑制缓冲层上的任何自然氧化膜促进形成具有鸟喙的场氧化物隔离区，通过硝化天然氧化物膜将天然氧化物膜转化成含氮膜如氮氧化硅。氧氮化硅膜可以通过将氧化物膜暴露于含氮等离子体，将氮离子注入到氧化膜中或者在含氮气氛中退火氧化膜来形成。在硝化步骤期间，天然氧化膜中的化学活性氧与结合在其中的氮结合。然后可以在缓冲层的硝化表面上形成含有氮化硅的顶部耐氧化层，并且在随后的氧化缓冲层的步骤中用作氧化掩模以形成场氧化物隔离区。通过在硝化步骤期间将化学活性氧与氮结合，通过限制化学活性氧的横向运输来抑制顶部抗氧化层下的侧向氧化。因此，顶部抗氧化层的掩蔽性能可以被增强并且用于形成具有短或不存在的鸟喙的场氧化物隔离区。

5. 发明授权

US5227322A Method for manufacturing a highly integrated semiconductor device having a capacitor of large capacitance 失效
标题翻译：制造具有大电容的电容器的高度集成的半导体器件的方法
公开(公告)号：US5227322A
公开(公告)日：1993-07-13
申请号：US868725
申请日：1992-04-14
申请人： Jae-hong Ko , Hee-seok Kim , Sung-tae Kim
发明人： Jae-hong Ko , Hee-seok Kim , Sung-tae Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L28/92
摘要： Disclosed is a method comprising forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an etching mask on the conductive layer, etching the conductive layer and defining the conductive layer into cell units; and forming a dielectric film and a second electrode or the first electrode. Also disclosed is a method comprising forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an etching mask on the conductive structure and etching the conductive structure; and forming a dielectric film and a second electrode on the first electrode. An insulating layer including pin holes such as a silicon nitride layer is formed on the conductive structure or the conductive layer; which is exposed under an oxidative atmosphere. The surface portion of the conductive structure or conductive layer is oxidized to form silicon oxide islands to be used as an etching mask. Since the method requires no specific process conditions, it is simple and extends the effective area of the cell capacitor, and is also applicable to various capacitor types.
摘要翻译：公开了一种方法，包括通过在半导体衬底上形成导电层形成第一电极，在导电层上形成蚀刻掩模，蚀刻导电层并将导电层限定为电池单元; 以及形成电介质膜和第二电极或第一电极。还公开了一种方法，包括通过在半导体衬底上形成导电结构形成第一电极，在导电结构上形成蚀刻掩模并蚀刻导电结构; 以及在所述第一电极上形成电介质膜和第二电极。在导电结构或导电层上形成包括诸如氮化硅层的针孔的绝缘层; 其在氧化气氛下暴露。导电结构或导电层的表面部分被氧化以形成用作蚀刻掩模的氧化硅岛。由于该方法不需要具体的工艺条件，简单且扩展了电池电容器的有效面积，也适用于各种电容器类型。

6. 发明授权

US08214617B2 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system 有权
标题翻译：避免单端口多库存储系统存在冲突的装置和方法
公开(公告)号：US08214617B2
公开(公告)日：2012-07-03
申请号：US12071910
申请日：2008-02-27
申请人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
发明人： Kyoung-june Min , Chan-min Park , Suk-jin Kim , Won-jong Lee , Kwon-taek Kwon , Hee-seok Kim
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836
摘要： Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.
摘要翻译：提供了一种避免银行冲突的方法和装置。通过将第一指令的执行定时改变为在第一指令的执行定时之前的定时，以访问指令来替换作为预测导致存储体冲突的访问指令之一的第一指令，不造成银行冲突。接下来，根据第一指令被调度为访问存储体的加载/存储单元访问存储体，并在第二指令的执行定时从存储体读出数据，然后允许加载/存储单元在第一指令的执行定时输入读数据。因此，尽管预测导致银行冲突的访问指令被分配给加载/存储单元，但是可以防止银行冲突，使得可以避免由于银行冲突的发生导致的性能下降。

7. 发明授权

US07153750B2 Methods of forming capacitors of semiconductor devices including silicon-germanium and metallic electrodes 有权
标题翻译：形成包括硅 - 锗和金属电极的半导体器件的电容器的方法
公开(公告)号：US07153750B2
公开(公告)日：2006-12-26
申请号：US10823352
申请日：2004-04-13
申请人： Eun-ae Chung , Ki-hyun Hwang , Jung-hwan Oh , Hyo-jung Kim , Seok-woo Nam , Won-sik Shin , U-in Chung , Young-sun Kim , Hee-seok Kim , Beom-jun Jin
发明人： Eun-ae Chung , Ki-hyun Hwang , Jung-hwan Oh , Hyo-jung Kim , Seok-woo Nam , Won-sik Shin , U-in Chung , Young-sun Kim , Hee-seok Kim , Beom-jun Jin
IPC分类号： H01L21/20
CPC分类号： H01L28/75 , H01L27/10852
摘要： A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySi1-xGex layer stacked on the metallic layer. Methods of forming these capacitors also are provided.
摘要翻译：半导体器件的电容器包括圆筒型电容器下电极，电介质层和上电极。上电极包括介于电介质层上的金属层和层叠在金属层上的掺杂多晶硅层1-x N层。还提供了形成这些电容器的方法。

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