专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06671796B1 Converting an arbitrary fixed point value to a floating point value 有权
标题翻译：将任意固定点值转换为浮点值
公开(公告)号：US06671796B1
公开(公告)日：2003-12-30
申请号：US09513494
申请日：2000-02-25
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
IPC分类号： G06F9302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/3838
摘要： A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.
摘要翻译：提供了一种方法和装置，用于在通用处理器上的浮点和固定点值之间执行有效的转换操作。这通过在通用处理器中提供用于将固定点值fx转换为浮点值f1的指令来实现。因此，本发明有利地提供了一种通用处理器，与通过需要多个指令执行相同功能的现有技术的通用处理器相比，能够以单个指令执行定点和浮点值之间的转换操作。因此，本发明的通用处理器允许在定点和浮点值之间更有效和更快的转换操作。

2. 发明授权

US06542988B1 Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file 有权
标题翻译：在将加载数据转发到寄存器文件之前，将加载指令和检索到的数据从加载缓冲区发送到附件
公开(公告)号：US06542988B1
公开(公告)日：2003-04-01
申请号：US09410842
申请日：1999-10-01
申请人： Marc Tremblay , Jeffrey Meng Wah Chan , Subramania Sudharsanan , Sharada Yeluri , Biyu Pan
发明人： Marc Tremblay , Jeffrey Meng Wah Chan , Subramania Sudharsanan , Sharada Yeluri , Biyu Pan
IPC分类号： G06F938
CPC分类号： G06F9/3855 , G06F9/3824 , G06F9/3851 , G06F9/3861 , G06F9/3875
摘要： A processor performs precise trap handling for out-of-order and speculative load instructions. It keeps track of the age of load instructions in a shared scheme that includes a load buffer and a load annex. All precise exceptions are detected in a T phase of a load pipeline. Data and control information concerning load operations that hit in the data cache are staged in a load annex during the A1, A2, A3, and T pipeline stages until all exceptions in the same or earlier instruction packet are detected. Data and control information from all other load instructions is staged in the load annex after the load data is retrieved. Before the load data is retrieved, the load instruction is kept in a load buffer. If an exception occurs, any load in the same instruction packet as the instruction causing the exception is canceled. Any load instructions that are “younger” than the instruction that caused the exception are also canceled. The age of load instructions is determined by tracking the pipe stages of the instruction. When a trap occurs, any load instruction with a non-zero age indicator is canceled.
摘要翻译：处理器执行精确的陷阱处理，用于无序和推测的加载指令。它跟踪包含加载缓冲区和加载附件的共享方案中的加载指令的时间。在负载管线的T相中检测到所有精确异常。在A1，A2，A3和T流水线阶段期间，有关在数据高速缓存中打入的加载操作的数据和控制信息在负载附件中分段，直到检测到相同或较早的指令包中的所有异常。在检索负载数据后，所有其他装载指令的数据和控制信息都将在装载附件中进行。在检索加载数据之前，将加载指令保存在加载缓冲区中。如果发生异常，与导致异常的指令相同的指令包中的任何负载都将被取消。任何比引起异常的指令“年轻”的加载指令也被取消。加载指令的年龄是通过跟踪指令的管道段来确定的。发生陷阱时，将取消带有非零年龄指示符的任何加载指令。

3. 发明授权

US06757820B2 Decompression bit processing with a general purpose alignment tool 有权
标题翻译：使用通用对齐工具进行减压位处理
公开(公告)号：US06757820B2
公开(公告)日：2004-06-29
申请号：US10356437
申请日：2003-01-31
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Marc Tremblay
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Marc Tremblay
IPC分类号： G06F9308
CPC分类号： G06F7/74 , G06F9/30018 , G06F9/30032
摘要： A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction. Both the first and the second instructions are pipelined to obtain an effective throughput of one instruction every cycle, respectively. As a result, bit extraction operations are performed very efficiently by the processor, thereby reducing the overall processing time required to compress and decompress multimedia data.
摘要翻译：提供了一种用于执行单指令位域提取并用于对通用处理器上的位序列中的多个前导零进行计数的方法和装置。快速位提取操作通过执行用于从任意偏移开始提取存储在处理器的两个或更多个源寄存器中的位序列的任意数量的比特并且将提取的比特存储在目的地寄存器中来实现。源寄存器和目标寄存器均由指令指定。此外，提供第二指令，用于对存储在处理器的两个或多个源寄存器中的位序列中的前导零的数目进行计数，然后将表示前导零数的二进制值存储在目的地寄存器中。源和目标寄存器又由第二条指令指定。第一和第二指令都被流水线分别获得每个周期一个指令的有效吞吐量。结果，处理器非常有效地执行比特提取操作，从而减少压缩和解压多媒体数据所需的整体处理时间。

4. 发明授权

US07587582B1 Method and apparatus for parallel arithmetic operations 有权
标题翻译：并行算术运算的方法和装置
公开(公告)号：US07587582B1
公开(公告)日：2009-09-08
申请号：US09640901
申请日：2000-08-16
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
IPC分类号： G06F7/38
CPC分类号： G06F9/30141 , G06F9/3001 , G06F9/3012 , G06F9/30145 , G06F9/3877
摘要： A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions: parallel multiply-add, conditional pick, parallel averaging, parallel power, parallel reciprocal square root and parallel shifts.
摘要翻译：提供了一种用于有效执行图形操作的方法和装置。这通过提供支持以下指令的任何组合的处理器来实现：并行乘法，条件选择，并行平均，并行功率，并行的平方根和平行移位。

5. 发明授权

US6163837A Writing of instruction results produced by instruction execution circuits to result destinations 有权
标题翻译：将指令执行电路产生的指令结果写入结果目的地
公开(公告)号：US6163837A
公开(公告)日：2000-12-19
申请号：US193487
申请日：1998-11-17
申请人： Jeffrey Meng Wah Chan , Subramania Sudharsanan , Marc Tremblay
发明人： Jeffrey Meng Wah Chan , Subramania Sudharsanan , Marc Tremblay
IPC分类号： G06F9/30 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30141 , G06F9/3838 , G06F9/3853 , G06F9/3869
摘要： Two instruction executions circuits C1 and C2, possibly pipelined, share a write port to write instruction results to their destinations. When both circuits have results available for writing in the same clock cycle, the write port is given to circuit C1. Circuit C2 gets the write port only when there is a bubble in the write back stage of circuit C1. Circuit C2 executes instructions that occur infrequently in an average program. Examples are division, reciprocal square root, and power computation instructions. Circuit C1 executes instructions that occur more frequently. Circuits C1 and C2 are part of a functional unit of a VLIW processor.
摘要翻译：两个指令执行电路C1和C2（可能是流水线的）共享写入端口，以将指令结果写入其目的地。当两个电路在相同的时钟周期内都有可用于写入的结果时，写入端口被提供给电路C1。电路C2仅在电路C1的写回级中有气泡时才得到写入端口。电路C2执行平均程序中不经常发生的指令。示例是除法，倒数平方根和功率计算指令。电路C1执行更频繁发生的指令。电路C1和C2是VLIW处理器的功能单元的一部分。

6. 发明授权

US06282637B1 Partially executing a pending atomic instruction to unlock resources when cancellation of the instruction occurs 有权
标题翻译：当发生指令取消时，部分执行挂起的原子指令来解锁资源
公开(公告)号：US06282637B1
公开(公告)日：2001-08-28
申请号：US09204760
申请日：1998-12-02
申请人： Jeffrey Meng Wah Chan , Marc Tremblay
发明人： Jeffrey Meng Wah Chan , Marc Tremblay
IPC分类号： G06F1300
CPC分类号： G06F9/3834 , G06F9/30021 , G06F9/3004 , G06F9/30087 , G06F9/3861
摘要： When an atomic instruction executed by a computer processor locks a memory location, the locking is performed before the processor has determined whether the instruction is to be executed to completion or canceled. The memory location is unlocked whether or not the instruction will be canceled. Since the locking operation can occur before it is known whether the instruction will be canceled, the reading of the memory location can also occur early, before it is known whether the instruction will be canceled.
摘要翻译：当由计算机处理器执行的原子指令锁定存储器位置时，在处理器确定是要执行指令以完成或取消之前执行锁定。无论指令是否被取消，存储位置都将被解锁。由于在知道指令是否被取消之前可以发生锁定操作，所以在知道指令是否被取消之前也可以及早发生存储器位置的读取。

7. 发明授权

US08745419B2 Logical power throttling of instruction decode rate for successive time periods 有权
标题翻译：连续时间段的逻辑功率节制指令解码速率
公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

8. 发明申请

US20120271941A1 METHOD AND SYSTEM FOR EFFICIENT AND EXHAUSTIVE URL CATEGORIZATION 有权
标题翻译：用于有效和排他性URL分类的方法和系统
公开(公告)号：US20120271941A1
公开(公告)日：2012-10-25
申请号：US13515079
申请日：2010-12-08
申请人： Olivier Mirandette , Marc Tremblay , Eric Melin
发明人： Olivier Mirandette , Marc Tremblay , Eric Melin
IPC分类号： G06F15/173
CPC分类号： H04L67/22 , G06F17/30876
摘要： The present method and system relate to categorizing URLs (Uniform Resource Locators) of web pages accessed by multiple users over an IP (Internet Protocol) based data network. The method and system collect real time data from IP data traffic occurring on the IP based data network, and extract parameters from the collected real time data, the parameters including an URL of a web page. The URL is processed by a rule based categorization engine, to associate a matching category to the URL of the web page. When no matching category is inferred, the URL is transferred to a semantic based categorization engine. A matching category is associated to the transferred URL by the semantic based categorization engine, based on a semantic analysis of the textual content extracted from the web page associated to the URL.
摘要翻译：本方法和系统涉及通过基于IP（基于因特网协议）的数据网络对由多个用户访问的网页的URL（统一资源定位符）进行分类。该方法和系统从基于IP的数据网络上发生的IP数据流量收集实时数据，并从收集的实时数据中提取参数，参数包括网页的URL。 URL由基于规则的分类引擎处理，以将匹配的类别与网页的URL相关联。当不推测出匹配类别时，URL被传送到基于语义的分类引擎。基于从与URL相关联的网页提取的文本内容的语义分析，基于语义的分类引擎将匹配的类别与传送的URL相关联。

9. 发明授权

US07878342B1 Clotheslines 有权
标题翻译：晒衣绳
公开(公告)号：US07878342B1
公开(公告)日：2011-02-01
申请号：US12218641
申请日：2008-07-17
申请人： Graham Louis Lewis , Marc Tremblay
发明人： Graham Louis Lewis , Marc Tremblay
IPC分类号： D06F53/00
CPC分类号： D06F53/00 , D06F53/04
摘要： A clothesline system comprises at least two separate cables that are independently tensionable through separate cable tensioning devices. The tension devices are attached together to provide for common, parallel movement of the separate cables though the cables are separately passed around separate pulleys at the both ends of the system. The two separate cables add strength to the system. The separate cables are preferably wound in left and right windings to prevent unraveling of the braid of the cable. By providing separate cables, assembly of the system is less complex as the two loops of cable are separate.
摘要翻译：晾衣绳系统包括通过单独的电缆张紧装置独立地张紧的至少两根单独的电缆。张力装置连接在一起，以提供单独的电缆的通常的平行移动，尽管电缆分别通过系统两端的分离的滑轮。两根单独的电缆增加了系统的强度。单独的电缆优选地缠绕在左右绕组中，以防止电缆的编织层松开。通过提供单独的电缆，系统的组装不太复杂，因为电缆的两个环路是分开的。

10. 发明申请

US20100268919A1 METHOD AND STRUCTURE FOR SOLVING THE EVIL-TWIN PROBLEM 有权
标题翻译：解决双向问题的方法与结构
公开(公告)号：US20100268919A1
公开(公告)日：2010-10-21
申请号：US12426550
申请日：2009-04-20
申请人： Shailender Chaudhry , Marc Tremblay
发明人： Shailender Chaudhry , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30112 , G06F9/30138 , G06F9/3838 , G06F9/384
摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
摘要翻译：在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。状态信息保存在每个n位寄存器的寄存器文件中。通过连续名称空间检测指令对其他指令的依赖性。状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式