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1. 发明授权

US06671796B1 Converting an arbitrary fixed point value to a floating point value 有权
标题翻译：将任意固定点值转换为浮点值
公开(公告)号：US06671796B1
公开(公告)日：2003-12-30
申请号：US09513494
申请日：2000-02-25
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
IPC分类号： G06F9302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/3838
摘要： A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.
摘要翻译：提供了一种方法和装置，用于在通用处理器上的浮点和固定点值之间执行有效的转换操作。这通过在通用处理器中提供用于将固定点值fx转换为浮点值f1的指令来实现。因此，本发明有利地提供了一种通用处理器，与通过需要多个指令执行相同功能的现有技术的通用处理器相比，能够以单个指令执行定点和浮点值之间的转换操作。因此，本发明的通用处理器允许在定点和浮点值之间更有效和更快的转换操作。

2. 发明授权

US06542988B1 Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file 有权
标题翻译：在将加载数据转发到寄存器文件之前，将加载指令和检索到的数据从加载缓冲区发送到附件
公开(公告)号：US06542988B1
公开(公告)日：2003-04-01
申请号：US09410842
申请日：1999-10-01
申请人： Marc Tremblay , Jeffrey Meng Wah Chan , Subramania Sudharsanan , Sharada Yeluri , Biyu Pan
发明人： Marc Tremblay , Jeffrey Meng Wah Chan , Subramania Sudharsanan , Sharada Yeluri , Biyu Pan
IPC分类号： G06F938
CPC分类号： G06F9/3855 , G06F9/3824 , G06F9/3851 , G06F9/3861 , G06F9/3875
摘要： A processor performs precise trap handling for out-of-order and speculative load instructions. It keeps track of the age of load instructions in a shared scheme that includes a load buffer and a load annex. All precise exceptions are detected in a T phase of a load pipeline. Data and control information concerning load operations that hit in the data cache are staged in a load annex during the A1, A2, A3, and T pipeline stages until all exceptions in the same or earlier instruction packet are detected. Data and control information from all other load instructions is staged in the load annex after the load data is retrieved. Before the load data is retrieved, the load instruction is kept in a load buffer. If an exception occurs, any load in the same instruction packet as the instruction causing the exception is canceled. Any load instructions that are “younger” than the instruction that caused the exception are also canceled. The age of load instructions is determined by tracking the pipe stages of the instruction. When a trap occurs, any load instruction with a non-zero age indicator is canceled.
摘要翻译：处理器执行精确的陷阱处理，用于无序和推测的加载指令。它跟踪包含加载缓冲区和加载附件的共享方案中的加载指令的时间。在负载管线的T相中检测到所有精确异常。在A1，A2，A3和T流水线阶段期间，有关在数据高速缓存中打入的加载操作的数据和控制信息在负载附件中分段，直到检测到相同或较早的指令包中的所有异常。在检索负载数据后，所有其他装载指令的数据和控制信息都将在装载附件中进行。在检索加载数据之前，将加载指令保存在加载缓冲区中。如果发生异常，与导致异常的指令相同的指令包中的任何负载都将被取消。任何比引起异常的指令“年轻”的加载指令也被取消。加载指令的年龄是通过跟踪指令的管道段来确定的。发生陷阱时，将取消带有非零年龄指示符的任何加载指令。

3. 发明授权

US07587582B1 Method and apparatus for parallel arithmetic operations 有权
标题翻译：并行算术运算的方法和装置
公开(公告)号：US07587582B1
公开(公告)日：2009-09-08
申请号：US09640901
申请日：2000-08-16
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Michael F. Deering , Marc Tremblay , Scott R. Nelson
IPC分类号： G06F7/38
CPC分类号： G06F9/30141 , G06F9/3001 , G06F9/3012 , G06F9/30145 , G06F9/3877
摘要： A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions: parallel multiply-add, conditional pick, parallel averaging, parallel power, parallel reciprocal square root and parallel shifts.
摘要翻译：提供了一种用于有效执行图形操作的方法和装置。这通过提供支持以下指令的任何组合的处理器来实现：并行乘法，条件选择，并行平均，并行功率，并行的平方根和平行移位。

4. 发明授权

US6163837A Writing of instruction results produced by instruction execution circuits to result destinations 有权
标题翻译：将指令执行电路产生的指令结果写入结果目的地
公开(公告)号：US6163837A
公开(公告)日：2000-12-19
申请号：US193487
申请日：1998-11-17
申请人： Jeffrey Meng Wah Chan , Subramania Sudharsanan , Marc Tremblay
发明人： Jeffrey Meng Wah Chan , Subramania Sudharsanan , Marc Tremblay
IPC分类号： G06F9/30 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30141 , G06F9/3838 , G06F9/3853 , G06F9/3869
摘要： Two instruction executions circuits C1 and C2, possibly pipelined, share a write port to write instruction results to their destinations. When both circuits have results available for writing in the same clock cycle, the write port is given to circuit C1. Circuit C2 gets the write port only when there is a bubble in the write back stage of circuit C1. Circuit C2 executes instructions that occur infrequently in an average program. Examples are division, reciprocal square root, and power computation instructions. Circuit C1 executes instructions that occur more frequently. Circuits C1 and C2 are part of a functional unit of a VLIW processor.
摘要翻译：两个指令执行电路C1和C2（可能是流水线的）共享写入端口，以将指令结果写入其目的地。当两个电路在相同的时钟周期内都有可用于写入的结果时，写入端口被提供给电路C1。电路C2仅在电路C1的写回级中有气泡时才得到写入端口。电路C2执行平均程序中不经常发生的指令。示例是除法，倒数平方根和功率计算指令。电路C1执行更频繁发生的指令。电路C1和C2是VLIW处理器的功能单元的一部分。

5. 发明授权

US06757820B2 Decompression bit processing with a general purpose alignment tool 有权
标题翻译：使用通用对齐工具进行减压位处理
公开(公告)号：US06757820B2
公开(公告)日：2004-06-29
申请号：US10356437
申请日：2003-01-31
申请人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Marc Tremblay
发明人： Subramania Sudharsanan , Jeffrey Meng Wah Chan , Marc Tremblay
IPC分类号： G06F9308
CPC分类号： G06F7/74 , G06F9/30018 , G06F9/30032
摘要： A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction. Both the first and the second instructions are pipelined to obtain an effective throughput of one instruction every cycle, respectively. As a result, bit extraction operations are performed very efficiently by the processor, thereby reducing the overall processing time required to compress and decompress multimedia data.
摘要翻译：提供了一种用于执行单指令位域提取并用于对通用处理器上的位序列中的多个前导零进行计数的方法和装置。快速位提取操作通过执行用于从任意偏移开始提取存储在处理器的两个或更多个源寄存器中的位序列的任意数量的比特并且将提取的比特存储在目的地寄存器中来实现。源寄存器和目标寄存器均由指令指定。此外，提供第二指令，用于对存储在处理器的两个或多个源寄存器中的位序列中的前导零的数目进行计数，然后将表示前导零数的二进制值存储在目的地寄存器中。源和目标寄存器又由第二条指令指定。第一和第二指令都被流水线分别获得每个周期一个指令的有效吞吐量。结果，处理器非常有效地执行比特提取操作，从而减少压缩和解压多媒体数据所需的整体处理时间。

6. 发明授权

US06654419B1 Block-based, adaptive, lossless video coder 有权
标题翻译：基于块的自适应无损视频编码器
公开(公告)号：US06654419B1
公开(公告)日：2003-11-25
申请号：US09561299
申请日：2000-04-28
申请人： Parthasarathy Sriram , Subramania Sudharsanan
发明人： Parthasarathy Sriram , Subramania Sudharsanan
IPC分类号： H04N718
CPC分类号： H04N19/507 , H04N19/105 , H04N19/136 , H04N19/174 , H04N19/18 , H04N19/436 , H04N19/46 , H04N19/51 , H04N19/61 , H04N19/91
摘要： Method and system for compression coding of a digitally represented video image. The video image is expressed as one or more data blocks in two or more frames, each block having a sequence of pixels with pixel values. Within each block of a frame, an intra-frame predictor index or inter-frame predictor index is chosen that predicts a pixel value as a linear combination of actual pixel values, drawn from one frame or from two or more adjacent frames. The predicted and actual pixel values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format in each frame. The compression ratios achieved by this coding approach compare favorably with, and may improve upon, the compression achieved by other compression methods. Several processes in determination of the compressed values can be performed in parallel to increase throughput or to reduce processing time.
摘要翻译：用于数字化视频图像的压缩编码的方法和系统。视频图像被表示为两个或更多个帧中的一个或多个数据块，每个块具有带有像素值的像素序列。在帧的每个块内，选择帧内预测器索引或帧间预测器索引，其将像素值预测为从一个帧或两个或更多个相邻帧绘制的实际像素值的线性组合。比较预测值和实际像素值，将预测值与实际值和最大预测值的和进行比较，以确定用于以压缩格式表示块中的每个像素值的值索引每一帧。通过该编码方法实现的压缩比与其它压缩方法实现的压缩有利地相比并且可以改进。可以并行执行确定压缩值的几个过程，以增加吞吐量或减少处理时间。

7. 发明授权

US5764698A Method and apparatus for efficient compression of high quality digital audio 失效
标题翻译：高效数字音频压缩方法及装置
公开(公告)号：US5764698A
公开(公告)日：1998-06-09
申请号：US175900
申请日：1993-12-30
申请人： Subramania Sudharsanan , Selvarathinam Suthakaran
发明人： Subramania Sudharsanan , Selvarathinam Suthakaran
IPC分类号： G10L19/02 , G10L19/00 , H03M7/30 , H04B1/66 , H03M7/34 , G01L3/02 , H04J15/00
CPC分类号： H04B1/665
摘要： A method and system for efficiently compressing a digital audio signal, wherein the digital audio signal includes a plurality of samples. Each of the samples are separated into a plurality of subbands. A signal to mask ratio (SMR) for each the subbands is predicted utilizing a model of relationships between energy values within each of the subbands and SMR values based on a predetermined psychoacoustic model. A number of are allocated bits in response to the predicted SMR and a preselected bit-rate. Then, each of the subbands are quantized based on the number of bits allocated, wherein the digital audio signal may be efficiently compressed.
摘要翻译：一种用于有效压缩数字音频信号的方法和系统，其中数字音频信号包括多个样本。每个样本被分成多个子带。基于预定的心理声学模型，使用每个子带内的能量值和SMR值之间的关系模型来预测每个子带的信号屏蔽比（SMR）。响应于预测的SMR和预选比特率，分配了多个比特。然后，基于分配的比特数来对每个子带进行量化，其中可以有效地压缩数字音频信号。

8. 发明授权

US07782953B2 Optimal encoding of motion compensated video 有权
标题翻译：运动补偿视频的最佳编码
公开(公告)号：US07782953B2
公开(公告)日：2010-08-24
申请号：US11428502
申请日：2006-07-03
申请人： Parthasarathy Sriram , Subramania Sudharsanan
发明人： Parthasarathy Sriram , Subramania Sudharsanan
IPC分类号： H04B1/66
CPC分类号： H04N19/567 , H04N19/103 , H04N19/107 , H04N19/136 , H04N19/137 , H04N19/147 , H04N19/176 , H04N19/19 , H04N19/51 , H04N19/56 , H04N19/61
摘要： Both distortion rate and bit-rate can be considered together when selecting a lowest cost motion estimation signal. A motion estimation signal is generated for each of the candidate motion vectors and candidate mode information vectors for a macroblock. An estimated amount of encoding bits is determined for each of the candidate motion vectors, candidate mode information vectors, and quantized coefficients. A bit-rate is computed based on the estimated amount of encoding bits. In addition, a current macroblock is reconstructed with each of the candidate vectors, and distortion measured between each of the reconstructions and the current macroblock. A sum is computed for each distortion measurement and corresponding bit-rate. The lowest sum represents the lowest cost motion estimation signal.
摘要翻译：当选择最低成本运动估计信号时，可以一起考虑失真率和比特率两者。针对宏块的每个候选运动矢量和候选模式信息向量生成运动估计信号。为每个候选运动矢量，候选模式信息向量和量化系数确定估计的编码比特量。基于估计的编码比特量来计算比特率。此外，利用每个候选向量重建当前宏块，并且在每个重建和当前宏块之间测量的失真。为每个失真测量和相应的比特率计算和。最低的和表示最低成本运动估计信号。

9. 发明授权

US07414550B1 Methods and systems for sample rate conversion and sample clock synchronization 有权
标题翻译：采样率转换和采样时钟同步的方法和系统
公开(公告)号：US07414550B1
公开(公告)日：2008-08-19
申请号：US11428304
申请日：2006-06-30
申请人： Subramania Sudharsanan
发明人： Subramania Sudharsanan
IPC分类号： H03M7/00
CPC分类号： H04J3/0632 , H03H17/0642 , H04L7/0029
摘要： The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples created or mixed using any of the standard audio frequencies in the set H={8, 11.025, 22.05, 44.1, 48, 96, and 192} kHz and played back using any other frequency from the set H. The synchronizer can be used where audio data are streamed or otherwise broadcast from, for example, the Internet, along with a system timestamp, and where this timestamp needs to be matched to the local audio clock for proper play-back. The same synchronizer can also be used for audio/video or video only synchronization.
摘要翻译：提出了组合通用采样率转换器和采样时钟同步器的架构。通用采样率转换器可以应用于例如使用集合H = {8,11.025,22.05,44.1,48,96和192} kHz中的任何标准音频创建或混合的音频样本，并播放使用来自集合H的任何其他频率。同步器可以用于音频数据被流式传输或以其他方式从例如因特网广播的位置以及系统时间戳，并且在该时间戳需要与本地音频时钟匹配的情况下适当回放。相同的同步器也可以用于音频/视频或视频同步。

10. 发明授权

US07321697B2 Block-based, adaptive, lossless image coder 有权
标题翻译：基于块的自适应，无损图像编码器
公开(公告)号：US07321697B2
公开(公告)日：2008-01-22
申请号：US10682550
申请日：2003-10-08
申请人： Subramania Sudharsanan , Parthasarathy Sriram
发明人： Subramania Sudharsanan , Parthasarathy Sriram
IPC分类号： G06K9/36
CPC分类号： H04N19/93 , H04N19/105 , H04N19/12 , H04N19/136 , H04N19/17 , H04N19/176 , H04N19/436 , H04N19/593 , H04N19/60 , H04N19/91
摘要： Method and system for lossless compression coding of a digitally represented image. The image is expressed as one or more blocks, each block having a sequence of pixels with binary pixel values. Within each block, a predictor index is chosen that predicts a pixel value as a linear combination of adjacent (actual) pixel values. The predicted and actual values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format. Use of the value index representation reduces the average number of bits needed to express each pixel value by an estimated 33-46 percent, reduces the time required for compression encoding by an estimated 4-6 percent, and reduces the time required for decompression by an estimated 49-61 percent. The compression ratios achieved by this coding approach compare favorably with, and sometimes improve upon, the compression achieved by several well known compression methods. Several processes in determination of the compressed values can be performed in parallel to increase throughput or to reduce processing time.
摘要翻译：用于数字化图像的无损压缩编码的方法和系统。图像被表示为一个或多个块，每个块具有具有二进制像素值的像素序列。在每个块内，选择预测器索引，其将像素值预测为相邻（实际）像素值的线性组合。比较预测值和实际值，将预测值与实际值和最大预测值的和进行比较，以确定用于表示压缩格式的块中的每个像素值的值索引。值索引表示的使用减少了将每个像素值表示为估计的33-46％所需的平均位数，将压缩编码所需的时间缩短了约4-6％，并减少了解压缩所需的时间估计为49-61％。通过这种编码方法实现的压缩比与通过几种公知的压缩方法实现的压缩有利地对应，并且有时改进。可以并行执行确定压缩值的几个过程，以增加吞吐量或减少处理时间。

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