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1. 发明授权

US06631138B1 Reduced pin-count 10Base-T MAC to transceiver interface 有权
标题翻译：引脚数10Base-T MAC到收发器接口
公开(公告)号：US06631138B1
公开(公告)日：2003-10-07
申请号：US09339637
申请日：1999-06-24
申请人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen , Bernard N. Daines , David Talaski
发明人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen , Bernard N. Daines , David Talaski
IPC分类号： H04J317
CPC分类号： H04L7/0008 , H04J3/0697
摘要： Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of nine times the number of ports, and the addition of each additional port requires only two more wires (pins).
摘要翻译：提供了一个10Base-T MAC到PHY接口，每个端口只需要两根电线（引脚），另外两根全球线：时钟线（引脚）和同步线（引脚）。通过时分复用实现与每个端口相关联的引脚数目的减少，其中每个时分复用引线组合来自常规七线接口的多个定义。因此，每个端口都有自己的一对相关联的时分复用电线（引脚），并且每个端口的添加只需要两根额外的电线。根据本发明的优选实施例，在10MHz的常规七线接口中通常在九条线路上传输的信息被时分复用到以40MHz传输数据的两条线（对应于两个引脚）四倍常规接口的速度。重要的是，这种复用是以端口为基础完成的。因此，MAC到收发器接口所需的引脚数量是端口数量的两倍，而不是端口数量的九倍，而每个附加端口的添加只需要两个电线（引脚）。

2. 发明授权

US07031333B1 Reduced pin count media independent interface 失效
标题翻译：减少针数媒体独立接口
公开(公告)号：US07031333B1
公开(公告)日：2006-04-18
申请号：US09089312
申请日：1998-06-02
申请人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen
发明人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen
IPC分类号： H04J3/00
CPC分类号： H04L12/66 , H04J3/0638
摘要： A system and method are disclosed for providing a method of communicating between a media access control (MAC) layer and a physical (PHY) layer. The method includes sending a 100 MHz time-division multiplexed signal on a receive data line and sending a time-division multiplexed receive control signal on a receive control line. A 100 MHz time-division multiplexed signal is sent on a transmit data line and a time-division multiplexed transmit control signal is sent on a transmit control line.
摘要翻译：公开了一种用于提供在媒体访问控制（MAC）层和物理（PHY）层之间进行通信的方法的系统和方法。该方法包括在接收数据线上发送100MHz时分复用信号，并在接收控制线上发送时分多路复用接收控制信号。在发送数据线上发送100MHz时分多路复用信号，在发送控制线上发送时分复用发送控制信号。

3. 发明授权

US5953345A Reduced pin-count 10Base-T MAC to transceiver interface 失效
公开(公告)号：US5953345A
公开(公告)日：1999-09-14
申请号：US89033
申请日：1998-06-02
申请人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen , Bernard N. Daines , David Talaski
发明人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen , Bernard N. Daines , David Talaski
IPC分类号： H04J3/06 , H04J3/16 , H04J3/17
CPC分类号： H04L7/0008 , H04J3/0697
摘要： Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of nine times the number of ports, and the addition of each additional port requires only two more wires (pins).

4. 发明授权

US06473424B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06473424B1
公开(公告)日：2002-10-29
申请号：US09204658
申请日：1998-12-02
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：提供了通过端口聚合来平衡数据传输的负载的方法，装置和系统。本发明的方法和装置基于负载分配端口分配，即通过组中的每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

5. 发明授权

US07480309B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US07480309B1
公开(公告)日：2009-01-20
申请号：US11075436
申请日：2005-03-07
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

6. 发明授权

US06934293B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06934293B1
公开(公告)日：2005-08-23
申请号：US10683222
申请日：2003-10-10
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/66
CPC分类号： H04L47/11 , H04L47/10 , H04L47/125 , H04L47/13 , H04L47/2441 , H04L47/30 , H04L49/90 , H04L49/901
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

7. 发明授权

US06667975B1 Port aggregation load balancing 有权
公开(公告)号：US06667975B1
公开(公告)日：2003-12-23
申请号：US10251605
申请日：2002-09-19
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

8. 发明授权

US6078532A Method and apparatus for improving performance of DRAM subsystems with SRAM overlays 有权
标题翻译：使用SRAM覆盖来提高DRAM子系统性能的方法和装置
公开(公告)号：US6078532A
公开(公告)日：2000-06-20
申请号：US241836
申请日：1999-02-01
申请人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
发明人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
IPC分类号： G11C7/22 , G11C11/00 , G11C11/418 , G11C11/419 , G11C7/00
CPC分类号： G11C11/005 , G11C11/418 , G11C11/419 , G11C7/22 , G11C2207/2281
摘要： A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.
摘要翻译：提供了减少或消除DRAM页面打开延迟或行访问延迟的影响的存储器系统。该系统使用DRAM和快速存储器，如SRAM。 SRAM用于存储来自数据块的数据的初始部分，并且DRAM的对应部分用于存储来自数据块的数据的终端部分。当请求访问数据块时，启动DRAM行访问过程。在延迟期间，当DRAM行访问过程发生时，来自所请求块的数据的初始部分从SRAM读出。大约在从SRAM读出初始数据的时间完成时，DRAM行访问过程完成，剩余部分数据从DRAM中读出。

9. 外观设计

USD254629S Sphygmometer 失效
公开(公告)号：USD254629S
公开(公告)日：1980-04-01
申请号：US844111
申请日：1977-10-20
申请人： David H. Yen
设计人： David H. Yen

10. 发明授权

US3999434A Temperature probe assembly and probe cover retainer 失效
标题翻译：温度探头组件和探头盖固定器
公开(公告)号：US3999434A
公开(公告)日：1976-12-28
申请号：US539798
申请日：1975-01-09
申请人： David H. Yen
发明人： David H. Yen
IPC分类号： G01K1/08
CPC分类号： G01K1/083
摘要： A temperature probe assembly including a housing with the temperature probe extending from one end with said end including means for retaining a probe cover. A probe cover ejector extends from the other end of the housing. Spring means within the housing serving to urge said probe and ejector in outwardly extended positions relative to said housing whereby said probe is urged into intimate contact with a probe cover and said ejector is urged in a retracted position. When the ejector is moved into said housing, it extends from the other end to release the retained cover.
摘要翻译：一种温度探测器组件，包括具有从一端延伸的温度探针的壳体，所述端部包括用于保持探针盖的装置。探头盖推出器从壳体的另一端延伸。壳体内的弹簧装置用于将所述探针和喷射器相对于所述壳体向外延伸的位置推动，由此所述探针被推动成与探针盖紧密接触，并且所述喷射器被推到缩回位置。当喷射器移动到所述壳体中时，其从另一端延伸以释放保持的盖。

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