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1. 再颁专利

USRE38820E1 Multi-protocol packet framing over an isochronous network 失效
标题翻译：通过同步网络进行多协议分组成帧
公开(公告)号：USRE38820E1
公开(公告)日：2005-10-11
申请号：US09285303
申请日：1998-07-02
申请人： Gregory L. Dejager , Erik R. Swenson
发明人： Gregory L. Dejager , Erik R. Swenson
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08 , H04Q11/04 , H04L12/52
CPC分类号： H04Q11/0478 , H04L29/06 , H04L69/18 , H04L69/324 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652
摘要： An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.
摘要翻译：集成电路具有用于从同步网络接收同步信息的等时网络端口。为了允许集成电路接收根据两种不同的封装协议（例如，HDLC和ATM）封装的信息，集成电路包括用于根据第一封装协议（例如，第一封装协议）打包信息的第一成帧器/去帧电路， HDLC）和用于防止根据第二打包协议（例如，ATM）打包的信息的第二成帧器/去帧电路。提供电路开关以根据网络帧的哪个时隙包含信息来使输入数据由适当的成帧器/去帧电路去帧化。一旦解帧，缓冲器管理器控制将信息存储在外部存储器中的环形缓冲器中。耦合到集成电路的主机总线上的设备然后可以经由集成电路的并行总线端口从圆形环形缓冲器读取信息。信息也可能通过并行总线端口，缓冲存储器端口到缓冲存储器，以及缓冲存储器通过缓冲存储器端口，通过适当的成帧器/去帧电路，通过同步网络端口相反的方向传递，以及到网络上

2. 发明授权

US5566203A Intelligent repeater functionality 失效
标题翻译：智能中继器功能
公开(公告)号：US5566203A
公开(公告)日：1996-10-15
申请号：US83963
申请日：1993-06-24
申请人： David C. Brief , Gregory L. DeJager , James R. Hamstra
发明人： David C. Brief , Gregory L. DeJager , James R. Hamstra
IPC分类号： H04B3/36 , H04L12/433 , H04L12/46 , H03H7/30 , H04J1/10
CPC分类号： H04B3/36 , H04L12/433 , H04L12/46 , Y10S370/906
摘要： A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.
摘要翻译：可以在通信系统中作为常规PHY或智能中继器操作的物理层（PHY）设备。 PHY器件支持四种可选模式，可通过使用微控制器对控制寄存器位进行编程使能。这些可选模式是：传递所有符号，启用噪声滤波器，通过违例符号和传递线路状态。在作为智能中继器的操作期间，启用所有符号，通过违规符号和通过线路状态模式。智能中继器允许对数据流中的错误进行编码和重复，而不必过滤到下游站。智能中继器还允许在不使用站管理软件的情况下重复线路状态。可以使用单个智能中继器来耦合两个站，或者可以连接多个智能中继器以形成可以连接的多端口中继器箱，以便于站之间更可靠的连接。

3. 发明授权

US06934293B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06934293B1
公开(公告)日：2005-08-23
申请号：US10683222
申请日：2003-10-10
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/66
CPC分类号： H04L47/11 , H04L47/10 , H04L47/125 , H04L47/13 , H04L47/2441 , H04L47/30 , H04L49/90 , H04L49/901
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

4. 发明授权

US06667975B1 Port aggregation load balancing 有权
公开(公告)号：US06667975B1
公开(公告)日：2003-12-23
申请号：US10251605
申请日：2002-09-19
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

5. 发明授权

US6078532A Method and apparatus for improving performance of DRAM subsystems with SRAM overlays 有权
标题翻译：使用SRAM覆盖来提高DRAM子系统性能的方法和装置
公开(公告)号：US6078532A
公开(公告)日：2000-06-20
申请号：US241836
申请日：1999-02-01
申请人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
发明人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
IPC分类号： G11C7/22 , G11C11/00 , G11C11/418 , G11C11/419 , G11C7/00
CPC分类号： G11C11/005 , G11C11/418 , G11C11/419 , G11C7/22 , G11C2207/2281
摘要： A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.
摘要翻译：提供了减少或消除DRAM页面打开延迟或行访问延迟的影响的存储器系统。该系统使用DRAM和快速存储器，如SRAM。 SRAM用于存储来自数据块的数据的初始部分，并且DRAM的对应部分用于存储来自数据块的数据的终端部分。当请求访问数据块时，启动DRAM行访问过程。在延迟期间，当DRAM行访问过程发生时，来自所请求块的数据的初始部分从SRAM读出。大约在从SRAM读出初始数据的时间完成时，DRAM行访问过程完成，剩余部分数据从DRAM中读出。

6. 发明授权

US06473424B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06473424B1
公开(公告)日：2002-10-29
申请号：US09204658
申请日：1998-12-02
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：提供了通过端口聚合来平衡数据传输的负载的方法，装置和系统。本发明的方法和装置基于负载分配端口分配，即通过组中的每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

7. 发明授权

US5875210A Method and apparatus for repeating data 失效
标题翻译：重复数据的方法和装置
公开(公告)号：US5875210A
公开(公告)日：1999-02-23
申请号：US801109
申请日：1997-02-13
申请人： David C. Brief , Gregory L. DeJager , James R. Hamstra
发明人： David C. Brief , Gregory L. DeJager , James R. Hamstra
IPC分类号： H04B3/36 , H04L12/433 , H04L12/46 , H04J1/16
CPC分类号： H04B3/36 , H04L12/433 , H04L12/46
摘要： A physical layer (PHY) device which can operate as a conventional PHY or as a repeater in a communication system. The PHY repeater supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. When the pass all symbols, pass violation symbols and pass line states modes are enabled, the PHY device operates as a "transparent" repeater. The repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The repeater also allows line states to be repeated without station management software. A single repeater may be used to couple two stations or multiple repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.
摘要翻译：物理层（PHY）设备，其可以作为通信系统中的常规PHY或中继器来操作。 PHY中继器支持四种可选模式，可通过使用微控制器对控制寄存器位进行编程使能。这些可选模式是：传递所有符号，启用噪声滤波器，通过违例符号和传递线路状态。当通过所有符号，通过违规符号和通过线路状态模式时，PHY设备作为“透明”中继器运行。中继器允许对数据流中的错误进行编码和重复，而不过滤到下游站。中继器还允许在没有站管理软件的情况下重复线路状态。单个中继器可以用于耦合两个站，或者多个中继器可以被连接以形成多端口中继器盒，其可以被连接以便于站之间更可靠的连接。

8. 发明授权

US5784404A Intelligent repeater functionality 失效
公开(公告)号：US5784404A
公开(公告)日：1998-07-21
申请号：US588971
申请日：1996-01-19
申请人： David C. Brief , Gregory L. DeJager , James R. Hamstra
发明人： David C. Brief , Gregory L. DeJager , James R. Hamstra
IPC分类号： H04B3/36 , H04L12/433 , H04L12/46 , G01R31/08
CPC分类号： H04B3/36 , H04L12/433 , H04L12/46 , Y10S370/906
摘要： A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.

9. 发明授权

US5533018A Multi-protocol packet framing over an isochronous network 失效
标题翻译：通过同步网络进行多协议分组成帧
公开(公告)号：US5533018A
公开(公告)日：1996-07-02
申请号：US361603
申请日：1994-12-21
申请人： Gregory L. DeJager , Erik R. Swenson
发明人： Gregory L. DeJager , Erik R. Swenson
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08 , H04Q11/04 , H04L12/52
CPC分类号： H04Q11/0478 , H04L29/06 , H04L2012/5615 , H04L2012/5616 , H04L2012/5652 , H04L69/18 , H04L69/324
摘要： An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory. A device residing on a host bus coupled to the integrated circuit may then read the information from the circular ring buffer via a parallel bus port of the integrated circuit. Information may also pass in the opposite direction from the parallel bus port, through a buffer memory port to the buffer memory, and from the buffer memory through the buffer memory port, through an appropriate framer/deframer circuit, through the isochronous network port, and onto the network.
摘要翻译：集成电路具有用于从同步网络接收同步信息的等时网络端口。为了允许集成电路接收根据两种不同的封装协议（例如，HDLC和ATM）封装的信息，集成电路包括用于根据第一封装协议（例如，第一封装协议）打包信息的第一成帧器/去帧电路， HDLC）和用于防止根据第二打包协议（例如，ATM）打包的信息的第二成帧器/去帧电路。提供电路开关以根据网络帧的哪个时隙包含信息来使输入数据由适当的成帧器/去帧电路去帧化。一旦解帧，缓冲器管理器控制将信息存储在外部存储器中的环形缓冲器中。耦合到集成电路的主机总线上的设备然后可以经由集成电路的并行总线端口从圆形环形缓冲器读取信息。信息也可能通过并行总线端口，缓冲存储器端口到缓冲存储器，以及缓冲存储器通过缓冲存储器端口，通过适当的成帧器/去帧电路，通过同步网络端口相反的方向传递，以及到网络上

10. 发明授权

US07480309B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US07480309B1
公开(公告)日：2009-01-20
申请号：US11075436
申请日：2005-03-07
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

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