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1. 发明授权

US06473424B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06473424B1
公开(公告)日：2002-10-29
申请号：US09204658
申请日：1998-12-02
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：提供了通过端口聚合来平衡数据传输的负载的方法，装置和系统。本发明的方法和装置基于负载分配端口分配，即通过组中的每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

2. 发明授权

US07480309B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US07480309B1
公开(公告)日：2009-01-20
申请号：US11075436
申请日：2005-03-07
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

3. 发明授权

US06934293B1 Port aggregation load balancing 有权
标题翻译：端口聚合负载均衡
公开(公告)号：US06934293B1
公开(公告)日：2005-08-23
申请号：US10683222
申请日：2003-10-10
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L12/56 , H04L12/66
CPC分类号： H04L47/11 , H04L47/10 , H04L47/125 , H04L47/13 , H04L47/2441 , H04L47/30 , H04L49/90 , H04L49/901
摘要： The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
摘要翻译：本发明的网络交换机和计算机可读介质基于负载分配端口分配，即通过组中每个端口转发的数据量。本发明的负载平衡优选是动态的，即来自给定流的分组可以根据每个端口的当前利用率在不同端口上转发。当选择新的端口来发送特定分组流时，完成这样的分组不能被顺序转发。这优选通过确保经过足够的时间段来允许给定流的所有分组在分配不同端口以发送相同流的分组之前由端口转发。本发明可以用于各种不同的网络环境和速度，包括10Base-T，100Base-T和千兆以太网以及其他网络环境。

4. 发明授权

US06667975B1 Port aggregation load balancing 有权
公开(公告)号：US06667975B1
公开(公告)日：2003-12-23
申请号：US10251605
申请日：2002-09-19
申请人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
发明人： Gregory L. DeJager , James R. Rivers , David H. Yen , Stewart Findlater , Scott A. Emery
IPC分类号： H04L1228
CPC分类号： H04L47/13 , H04L47/10 , H04L47/11 , H04L47/125 , H04L49/90 , H04L49/9094
摘要： Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.

5. 发明授权

US6078532A Method and apparatus for improving performance of DRAM subsystems with SRAM overlays 有权
标题翻译：使用SRAM覆盖来提高DRAM子系统性能的方法和装置
公开(公告)号：US6078532A
公开(公告)日：2000-06-20
申请号：US241836
申请日：1999-02-01
申请人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
发明人： James P. Rivers , Gregory L. DeJager , David H. Yen , Stewart Findlater , Bradley Erickson , Scott A. Emery
IPC分类号： G11C7/22 , G11C11/00 , G11C11/418 , G11C11/419 , G11C7/00
CPC分类号： G11C11/005 , G11C11/418 , G11C11/419 , G11C7/22 , G11C2207/2281
摘要： A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.
摘要翻译：提供了减少或消除DRAM页面打开延迟或行访问延迟的影响的存储器系统。该系统使用DRAM和快速存储器，如SRAM。 SRAM用于存储来自数据块的数据的初始部分，并且DRAM的对应部分用于存储来自数据块的数据的终端部分。当请求访问数据块时，启动DRAM行访问过程。在延迟期间，当DRAM行访问过程发生时，来自所请求块的数据的初始部分从SRAM读出。大约在从SRAM读出初始数据的时间完成时，DRAM行访问过程完成，剩余部分数据从DRAM中读出。

6. 发明授权

US5459854A Method for optimizing software for any one of a plurality of variant architectures 失效
标题翻译：用于优化多个变体架构中的任何一个的软件的方法
公开(公告)号：US5459854A
公开(公告)日：1995-10-17
申请号：US727824
申请日：1991-07-09
申请人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
发明人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
IPC分类号： G06F9/445 , G06F12/02 , G06F9/24 , G06F15/177
CPC分类号： G06F12/023 , G06F9/44547
摘要： A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
摘要翻译：一种方法允许设计人员为多种不同的主机架构实现软件，而不会过多地使用主机内存，也不会牺牲可用的变体架构的高端版本的功能。该方法基于提供软件的初始化模块来主机存储器。初始化模块的一部分确定主机架构。基于确定的主机架构，初始化模块的不需要的部分被释放，并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。然后根据重定位更新程序所需部分中的任何位置相关条目。初始化模块包括多个代码块，每个代码块针对特定的变体架构被优化。当识别主机的变体架构时，选择对识别的主机优化的代码块，并且释放其他代码块。然后重新定位所选择的块以优化主机内存使用。

7. 发明授权

US5530874A Network adapter with an indication signal mask and an interrupt signal mask 失效
标题翻译：具有指示信号掩码和中断信号掩码的网络适配器
公开(公告)号：US5530874A
公开(公告)日：1996-06-25
申请号：US012561
申请日：1993-02-02
申请人： Scott A. Emery , Brian Petersen , W. Paul Sherer
发明人： Scott A. Emery , Brian Petersen , W. Paul Sherer
IPC分类号： G06F13/00 , G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： Indication and interrupt signals generated by a network adapter representing asynchronous events are managed by a host system. The network adapter includes a first mask logic for selectively disabling the indication signals from being stored in a first memory location by the host writing to a first mask register. A second mask logic which is coupled to the first memory location also selectively disables the indication signals from being stored in a second memory location creating two levels of status information. The indication signals may also be disabled from being stored in the second memory location responsive to the host writing to a second mask register. The first memory location may be read from the host in order to determine whether a network event occurred during an interrupt service routine, while interrupt means generates an interrupt signal to the host responsive to the value in the second memory location. A third level of control is provided by an internal counter which allows for automatic enabling and/or disabling of a plurality of indications and interrupts with and without explicit commands in the host driver subroutines.
摘要翻译：由代表异步事件的网络适配器产生的指示和中断信号由主机系统管理。网络适配器包括第一屏蔽逻辑，用于通过主机向第一屏蔽寄存器写入来选择性地禁用指示信号存储在第一存储器位置。耦合到第一存储器位置的第二掩模逻辑还选择性地禁止指示信号被存储在创建两级状态信息的第二存储器位置中。响应于主机向第二屏蔽寄存器的写入，也可以禁止指示信号存储在第二存储单元中。可以从主机读取第一存储器位置，以便确定在中断服务程序期间是否发生网络事件，而中断装置响应于第二存储器位置中的值产生对主机的中断信号。第三级控制由内部计数器提供，其允许在主机驱动程序子程序中使用和不使用显式命令来自动启用和/或禁用多个指示和中断。

8. 发明授权

US06587936B1 Multi-bank memory access method and apparatus 失效
标题翻译：多组存储器存取方法及装置
公开(公告)号：US06587936B1
公开(公告)日：2003-07-01
申请号：US09790295
申请日：2001-02-21
申请人： James P. Rivers , Scott A. Emery
发明人： James P. Rivers , Scott A. Emery
IPC分类号： G06F1202
CPC分类号： G11C7/10 , G06F12/0215 , G11C7/1042 , G11C7/22
摘要： Data is stored in a memory in a manner which eliminates dead time which occurs when the number of words in a page which are read-out are insufficient to provide enough time for simultaneously opening the next page. If the length of a frame being stored in memory is not an exact integral multiple of words in a page, a penultimate (or earlier) page is written with fewer words than the page can hold. This allows additional words to be placed into the last page, sufficient to provide every page used for storing a frame at least a number of words equal to the number of clock cycles needed for opening a next page.
摘要翻译：数据以消除死读时间的方式存储在存储器中，当读出的页面中的字数不足以提供足够的时间同时打开下一页时。如果存储在存储器中的帧的长度不是页面中单词的确切整数倍，则倒数第（或更早）页面被写入具有比页面可容纳的更少的单词。这允许将附加字放置在最后一页中，足以提供用于存储帧的每一页至少多个字数等于打开下一页所需的时钟周期数。

9. 发明授权

US5600823A Method for optimizing software for any one of a plurality of variant architectures 失效
标题翻译：用于优化多个变体架构中的任何一个的软件的方法
公开(公告)号：US5600823A
公开(公告)日：1997-02-04
申请号：US417840
申请日：1995-04-06
申请人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
发明人： W. Paul Sherer , Glenn W. Connery , Scott A. Emery
IPC分类号： G06F9/445 , G06F12/02 , G06F15/177
CPC分类号： G06F12/023 , G06F9/44547
摘要： A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
摘要翻译：一种方法允许设计人员为多种不同的主机架构实现软件，而不会过多地使用主机内存，也不会牺牲可用的变体架构的高端版本的功能。该方法基于提供软件的初始化模块来主机存储器。初始化模块的一部分确定主机架构。基于确定的主机架构，初始化模块的不需要的部分被释放，并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。然后根据重定位更新程序所需部分中的任何位置相关条目。初始化模块包括多个代码块，每个代码块针对特定的变体架构被优化。当识别主机的变体架构时，选择对识别的主机优化的代码块，并且释放其他代码块。然后重新定位所选择的块以优化主机内存使用。

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