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1. 发明授权

US08825730B1 Matrix decomposition using dataflow techniques 有权
标题翻译：使用数据流技术进行矩阵分解
公开(公告)号：US08825730B1
公开(公告)日：2014-09-02
申请号：US13252562
申请日：2011-10-04
申请人： Steven Perry , Coleman C. Cheung
发明人： Steven Perry , Coleman C. Cheung
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： Efficient and scalable circuitry for performing Cholesky decomposition is based on a dataflow style architecture which uses self-timed circuitry and eliminates the need for complicated state machines. Calculations are ordered such that partial sums of products are created in parallel subject to data dependency requirements, allowing a single accumulator to perform the summation. A Vector FIFO receives a partial sum of products from a vector processing engine. A Feedback FIFO stores partial results and feeds the partial results back to the data path based on signals from a dataflow controller. The circuitry is flexible to allow different matrix sizes, speed grades, and target frequencies without recompilation.
摘要翻译：用于执行Cholesky分解的高效和可扩展的电路基于使用自定时电路的数据流风格架构，并且不需要复杂的状态机。按照数据依赖性要求并行创建产品的部分和来进行计算，允许单个累加器执行求和。向量FIFO从矢量处理引擎接收产品的部分和。反馈FIFO存储部分结果，并且基于来自数据流控制器的信号将部分结果反馈给数据路径。该电路灵活，允许不同的矩阵尺寸，速度等级和目标频率，无需重新编译。

2. 发明授权

US09176912B2 Processor to message-based network interface using speculative techniques 有权
标题翻译：处理器以基于消息的网络接口采用投机技术
公开(公告)号：US09176912B2
公开(公告)日：2015-11-03
申请号：US13369727
申请日：2012-02-09
申请人： Steven Perry , Gareth Duncan
发明人： Steven Perry , Gareth Duncan
IPC分类号： G06F13/38 , H04L12/861
CPC分类号： G06F13/385 , G06F2213/3808 , H04L49/90
摘要： Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.
摘要翻译：提供了一种方法和系统，用于耦合到处理器的消息网络接口单元（消息接口单元），其用于允许处理器向硬件单元发送消息。还提供了一种方法和系统，用于耦合到处理器的消息接口单元，其用于允许处理器从硬件单元接收消息。本文描述的消息网络接口单元可以允许执行数据密集型实时应用，其需要基本上低的消息响应延迟和基本上高的消息吞吐量。

3. 发明授权

US08615543B1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US08615543B1
公开(公告)日：2013-12-24
申请号：US13166119
申请日：2011-06-22
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

4. 发明授权

US08402400B1 Method and apparatus for implementing a processor interface block with an electronic design automation tool 有权
标题翻译：一种用电子设计自动化工具实现处理器接口块的方法和装置
公开(公告)号：US08402400B1
公开(公告)日：2013-03-19
申请号：US12932140
申请日：2011-02-18
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
摘要翻译：用于在现场可编程门阵列（FPGA）上生成系统设计的电气设计自动化（EDA）工具包括一个库，其包括由设计者可选择的处理器接口块，以表示处理器可访问的设计中的组件。 EDA工具还包括处理器接口电路生成单元，用于在设计中自动生成电路以支持处理器接口块，而无需设计者的输入。

5. 发明授权

US07467176B2 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US07467176B2
公开(公告)日：2008-12-16
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在乘法累加（MAC）块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

6. 发明授权

US07290237B2 Method for programming a mask-programmable logic device and device so programmed 有权
标题翻译：用于编程掩码可编程逻辑器件和如此编程的器件的方法
公开(公告)号：US07290237B2
公开(公告)日：2007-10-30
申请号：US10875256
申请日：2004-06-23
申请人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
发明人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.
摘要翻译：可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。为了便于迁移，可以创建成对的设备之间的固定映射。

7. 发明授权

US07216330B1 Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices by registering a user specified procedure 有权
标题翻译：用于通过注册用户指定的程序来扩展用于在可编程逻辑器件上设计系统的工具的能力的方法和装置
公开(公告)号：US07216330B1
公开(公告)日：2007-05-08
申请号：US10413081
申请日：2003-04-14
申请人： Steven Perry , Gregor Nixon , Alasdair Scott , Philippe Marti
发明人： Steven Perry , Gregor Nixon , Alasdair Scott , Philippe Marti
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.
摘要翻译：根据本发明的第一实施例公开了一种在PLD上设计系统的方法。优化了逻辑设计。来自逻辑设计的逻辑电路映射到PLD上的资源。至少一些资源通过使用用户指定的过程被安装到PLD上的位置上。

8. 发明申请

US20060275185A1 Flow control through plural, parallel connecting channels to/from a manifold 有权
标题翻译：通过多个并联连接通道/从歧管进行流量控制
公开(公告)号：US20060275185A1
公开(公告)日：2006-12-07
申请号：US11400056
申请日：2006-04-07
申请人： Anna Tonkovich , Bin Yang , Steven Perry , Sean Fitzgerald , Ravi Arora , Robert Luzenski , Thomas Yuschak
发明人： Anna Tonkovich , Bin Yang , Steven Perry , Sean Fitzgerald , Ravi Arora , Robert Luzenski , Thomas Yuschak
IPC分类号： B01J19/00 , H01L31/00 , B01L3/02
CPC分类号： F28F13/06 , B01J19/0093 , B01J2219/00783 , B01J2219/00822 , B01J2219/00824 , B01J2219/00833 , B01J2219/00835 , B01J2219/0086 , B01J2219/00889 , B01J2219/00891 , B01J2219/00995 , B01L3/502746 , B01L2200/027 , B01L2300/0864 , B01L2300/0887 , B01L2400/0487 , B01L2400/086 , F28F2260/02 , Y10T137/0396
摘要： The invention provides apparatuses and techniques for controlling flow between a manifold and two or more connecting microchannels. Flow between plural connecting microchannels, that share a common manifold, can be made more uniform by the use of flow straighteners and distributors that equalize flow in connecting channels. Alternatively, flow can be made more uniform by sections of narrowed diameter within the channels. Methods of making apparatus and methods of conducting unit operations in connecting channels are also described.
摘要翻译：本发明提供用于控制歧管和两个或更多个连接微通道之间的流动的装置和技术。通过使用均衡连接通道中的流动的流平衡器和分配器，可以使共享共同歧管的多个连接微通道之间的流动更均匀。或者，可以通过通道内的变窄直径的部分使流动更均匀。还描述了在连接通道中进行单元操作的装置和方法的方法。

9. 发明授权

US07076751B1 Chip debugging using incremental recompilation 失效
公开(公告)号：US07076751B1
公开(公告)日：2006-07-11
申请号：US10351017
申请日：2003-01-24
申请人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
发明人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5054 , G06F17/5077
摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

10. 发明申请

US20060016215A1 Distillation process using microchannel technology 有权
标题翻译：蒸馏工艺采用微通道技术
公开(公告)号：US20060016215A1
公开(公告)日：2006-01-26
申请号：US10898687
申请日：2004-07-23
申请人： Anna Tonkovich , Wayne Simmons , Laura Silva , Dongming Qiu , Steven Perry , Thomas Yuschak
发明人： Anna Tonkovich , Wayne Simmons , Laura Silva , Dongming Qiu , Steven Perry , Thomas Yuschak
IPC分类号： F25J3/00 , F25J5/00
CPC分类号： F25J3/04896 , B01D3/146 , C07C7/04 , F25J3/0209 , F25J3/0219 , F25J3/0233 , F25J3/0238 , F25J3/0242 , F25J3/0247 , F25J3/0295 , F25J3/04624 , F25J3/04975 , F25J5/007 , F25J2200/80 , F25J2200/90 , F25J2210/12 , F25J2215/62 , F25J2270/90 , F25J2290/20 , F25J2290/42 , F25J2290/44 , Y10S62/902 , C07C11/02 , C07C9/04
摘要： The disclosed invention relates to a process for distilling a fluid mixture in a microchannel distillation unit, the microchannel distillation unit comprising a plurality of microchannel distillation sections, the fluid mixture comprising a more volatile component and a less volatile component, the process comprising: flowing a vapor phase of the fluid mixture in a first microchannel distillation section in contact with a liquid phase of the fluid mixture, part of the more volatile component transferring from the liquid phase to the vapor phase to form a more volatile component rich vapor phase, part of the less volatile component transferring from the vapor phase to the liquid phase to form a less volatile component rich liquid phase; separating the more volatile component rich vapor phase from the less volatile component rich liquid phase; flowing the less volatile component rich liquid phase to another microchannel distillation section upstream from the first microchannel distillation section; and flowing the more volatile rich vapor phase to another microchannel distillation section downstream from the first microchannel distillation section.
摘要翻译：所公开的本发明涉及一种在微通道蒸馏单元中蒸馏流体混合物的方法，所述微通道蒸馏单元包括多个微通道蒸馏段，所述流体混合物包含更易挥发组分和较不易挥发组分，所述方法包括：在与液体混合物的液相接触的第一微通道蒸馏部分中的流体混合物的气相，部分更易挥发的组分从液相转移到气相以形成更易挥发的组分富气相，部分挥发性较低的组分从气相转移到液相以形成较不易挥发的组分富液相; 将较易挥发的组分丰富的气相与较不易挥发的富含组分的液相分离; 将较不易挥发的组分富液相流向第一微通道蒸馏段上游的另一微通道蒸馏段; 并将更易挥发的富气相流动到第一微通道蒸馏段下游的另一微通道蒸馏段。

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