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    • 6. 发明授权
    • Wearable auscultation system and method
    • 可佩戴听诊系统及方法
    • US07976480B2
    • 2011-07-12
    • US11008430
    • 2004-12-09
    • Lillana GrajalesMark W. CholewczynskiMark A. KrizikLawrence E. LachIon V. Nicolasescu
    • Lillana GrajalesMark W. CholewczynskiMark A. KrizikLawrence E. LachIon V. Nicolasescu
    • A61B7/00
    • A61B5/6804A61B7/04
    • A method and system for monitoring physiological parameters is useful for remote auscultation of the heart and lungs. The system includes an acoustic sensor (105) that has a stethoscopic cup (305). A membrane (325) is positioned adjacent to a first end of the stethoscopic cup (305), and an impedance matching element (335) is positioned adjacent to the membrane (325). The element (335) provides for acoustic impedance matching with a body such as a human torso. A microphone (315) is positioned near the other end of the stethoscopic cup (305) so as to detect sounds from the body. A signal-conditioning module (110) is then operatively connected to the acoustic sensor (105), and a wireless transceiver (115) is operatively connected to the signal-conditioning module (110). Auscultation can then occur at a remote facility that receives signals sent from the transceiver (115).
    • 用于监测生理参数的方法和系统对于心脏和肺的远程听诊是有用的。 该系统包括具有听诊器杯(305)的声学传感器(105)。 膜(325)定位成与听诊器杯(305)的第一端相邻,并且阻抗匹配元件(335)邻近膜(325)定位。 元件(335)提供与身体(例如人体躯干)的声阻抗匹配。 麦克风(315)位于听诊器杯(305)的另一端附近,以便检测来自身体的声音。 信号调节模块(110)然后可操作地连接到声学传感器(105),并且无线收发器(115)可操作地连接到信号调节模块(110)。 然后可以在接收从收发器(115)发送的信号的远程设施处进行听诊。
    • 8. 发明授权
    • Cascade FET logic circuits
    • 级联FET逻辑电路
    • US4877976A
    • 1989-10-31
    • US257897
    • 1988-10-13
    • Lawrence E. LachMikiharu Ohoka
    • Lawrence E. LachMikiharu Ohoka
    • H03K19/094H03K19/0952
    • H03K19/0952H03K19/09403
    • A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field effect transistors having a second threshold voltage, for providing a logic operation. The second threshold voltage is less than zero and is less than the first threshold voltage. The group III-V digital logic circuit can be formed as an integrated circuit on, in particular, a GaAs substrate. The field effect transistor can be either a metal semiconductor field effect transistor or a junction field effect transistor.
    • 一种III-V族数字逻辑电路,其包括至少两个增强型金属半导体场效应晶体管和一个具有第一阈值电压的负载元件或两个第一类型场效应晶体管和具有第二阈值电压的两个第二类型场效应晶体管, 用于提供逻辑运算。 第二阈值电压小于零并且小于第一阈值电压。 III-V族数字逻辑电路可以形成为特别是GaAs衬底上的集成电路。 场效应晶体管可以是金属半导体场效应晶体管或结型场效应晶体管。