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1. 发明授权

US06330649B1 Multiprocessor digital data processing system 失效
标题翻译：多处理器数字数据处理系统
公开(公告)号：US06330649B1
公开(公告)日：2001-12-11
申请号：US09375042
申请日：1999-08-16
申请人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
IPC分类号： G06F1214
CPC分类号： G06F9/5016 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F12/126 , G06F2212/272 , H04L12/4637 , H04L45/04
摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.
摘要翻译：多处理器数字数据处理系统包括以环的分层布置的多个处理单元。系统选择性地分配存储并且响应于由单元产生的访问请求而将独占数据副本从单元移动到单元。采用路由元素来选择性地广播环上的数据访问请求，更新和传送。

2. 发明授权

US5960461A Multiprocessor digital data processing system/shared memory multiprocessor system and method of operation 失效
标题翻译：多处理器数字数据处理系统/共享内存多处理器系统及操作方法
公开(公告)号：US5960461A
公开(公告)日：1999-09-28
申请号：US403308
申请日：1995-03-14
申请人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
IPC分类号： G06F15/177 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , H04L12/46 , H04L12/56 , G06F12/14
CPC分类号： G06F9/5016 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , H04L12/4637 , H04L45/04 , G06F12/126 , G06F2212/272
摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.
摘要翻译：多处理器数字数据处理系统包括以环的分层布置的多个处理单元。系统选择性地分配存储并且响应于由单元产生的访问请求而将独占数据副本从单元移动到单元。采用路由元素来选择性地广播环上的数据访问请求，更新和传送。

3. 发明授权

US06694412B2 Multiprocessor digital data processing system 失效
标题翻译：多处理器数字数据处理系统
公开(公告)号：US06694412B2
公开(公告)日：2004-02-17
申请号：US09967404
申请日：2001-09-28
申请人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
IPC分类号： G06F1208
CPC分类号： G06F9/5016 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F12/126 , G06F2212/272 , H04L12/4637 , H04L45/04
摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.
摘要翻译：多处理器数字数据处理系统包括以环的分层布置的多个处理单元。系统选择性地分配存储并且响应于由单元产生的访问请求而将独占数据副本从单元移动到单元。采用路由元素来选择性地广播环上的数据访问请求，更新和传送。

4. 发明授权

US5055999A Multiprocessor digital data processing system 失效
标题翻译：多处理器数字数据处理系统
公开(公告)号：US5055999A
公开(公告)日：1991-10-08
申请号：US136930
申请日：1987-12-22
申请人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Linda O. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
IPC分类号： G06F15/177 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , H04L12/46 , H04L12/56
CPC分类号： G06F9/5016 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , H04L12/4637 , H04L45/04 , G06F12/126 , G06F2212/272
摘要： A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

5. 发明授权

US5297265A Shared memory multiprocessor system and method of operation thereof 失效
标题翻译：共享内存多处理器系统及其操作方法
公开(公告)号：US5297265A
公开(公告)日：1994-03-22
申请号：US370341
申请日：1989-06-22
申请人： Steven J. Frank , Henry Burkhardt, III , Linda Q. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Linda Q. Lee , Nathan Goodman , Benson I. Margulies , Frederick D. Weber
IPC分类号： G06F15/177 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , H04L12/46 , H04L12/56 , G06F1/00
CPC分类号： G06F9/5016 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , H04L12/4637 , H04L45/04 , G06F12/126 , G06F2212/272
摘要： A digital data processing apparatus has plural processing cells, each with a memory element that stores data page made up of plural subpages. At least one of the cells includes a CPU that can request access to a data subpage. A memory manager responds to selected data access requests by (i) allocating, within the memory local to the requesting CPU, exclusive physical storage space for a data page associated with the requested subpage, and (ii) storing the requested subpage in that allocated space. The apparatus recombines data pages and deallocates them on the basis of usage and access state. The apparatus also accesses data asynchronously with respect to execution of instructions by the CPU.
摘要翻译：数字数据处理装置具有多个处理单元，每个处理单元具有存储由多个子页构成的数据页的存储元件。至少一个单元包括可请求访问数据子页面的CPU。存储器管理器通过（i）在请求CPU本地的存储器内分配用于与所请求的子页面相关联的数据页面的专用物理存储空间，以及（ii）在所分配的空间中存储所请求的子页面来响应所选择的数据访问请求。该装置重新组合数据页面，并根据使用情况和访问状态解除分配。该装置还相对于CPU执行指令而异步访问数据。

6. 发明授权

US5251308A Shared memory multiprocessor with data hiding and post-store 失效
标题翻译：具有数据隐藏和后期存储的共享内存多处理器
公开(公告)号：US5251308A
公开(公告)日：1993-10-05
申请号：US370287
申请日：1989-06-22
申请人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , Benson I. Margulies , Frederick D. Weber , Linda Q. Lee , Glen Dudek , William F. Mann , Edward N. Kittlitz , Ruth Shelley
发明人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , Benson I. Margulies , Frederick D. Weber , Linda Q. Lee , Glen Dudek , William F. Mann , Edward N. Kittlitz , Ruth Shelley
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , G06F15/173 , H04L12/46 , H04L12/56 , G06F13/00
CPC分类号： G06F9/5016 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0772 , G06F12/0811 , G06F12/0817 , G06F12/10 , G06F15/17337 , G06F9/3005 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3865 , G06F9/468 , G06F9/52 , H04L12/4637 , H04L45/04 , G06F12/126 , G06F2212/272
摘要： A digital data processing system includes a plurality of central processor units which share and access a common memory through a memory management element. The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datum's existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements, each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.
摘要翻译：数字数据处理系统包括通过存储器管理元件共享和访问公共存储器的多个中央处理器单元。存储器管理元件尤其允许以至少两种模式访问公共存储器中的数据。在第一模式中，所有请求访问存储在存储器中的给定数据的所有中央处理单元用信号表示基准存在。在第二模式中，只有请求访问驻留数据的所选择的中央处理单元被通知其存在，而请求访问基准的其他中央处理单元被发信号通知其不存在。公共存储器可以包括多个独立的存储器元件，每个独立的存储器元件耦合到相应的一个中央处理单元并与之相关联。中央处理单元可以包括用于实现将存储在其关联的存储器元件中的数据的副本传送到与另一中央处理单元相关联的存储元件的后存储元件。

7. 发明授权

US5119481A Register bus multiprocessor system with shift 失效
标题翻译：寄存器总线多处理器系统
公开(公告)号：US5119481A
公开(公告)日：1992-06-02
申请号：US696291
申请日：1991-04-26
申请人： Steven J. Frank , Henry Burkhardt, III , Frederick D. Weber
发明人： Steven J. Frank , Henry Burkhardt, III , Frederick D. Weber
IPC分类号： G06F15/173 , H04L12/433
CPC分类号： H04L12/433 , G06F15/17337
摘要： A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.
摘要翻译：数字数据处理装置包括传送数字信息包的移位寄存器总线。该总线具有以环形配置串联连接的多个数字存储和传送级。每个包括至少一个存储器元件的多个处理单元通过总线以环形配置连接，每个单元与总线的相关分级子集通信。至少一个处理单元包括单元互连，其执行基于在该分组中识别的数据与存储在所述相关联的存储器元件中的一个或多个数据之间的关联（如果有的话）修改，提取，复制和传送分组中的至少一个。小区互连响应所应用的数字时钟周期信号，用于在执行修改，提取，复制和传送操作的同时以响应于数字时钟周期速率的速率在总线的连续级中同时传送至少一个选定分组。

8. 发明授权

US5335325A High-speed packet switching apparatus and method 失效
标题翻译：高速分组交换设备及方法
公开(公告)号：US5335325A
公开(公告)日：1994-08-02
申请号：US499182
申请日：1990-03-26
申请人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , William F. Mann
发明人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , William F. Mann
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , H04L12/46 , H04L12/56 , G06F13/14
CPC分类号： H04L12/5601 , G06F11/004 , G06F11/0724 , G06F11/0766 , G06F12/0811 , G06F12/0817 , G06F12/10 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3865 , G06F9/3867 , G06F9/3885 , G06F9/468 , G06F9/5016 , G06F9/52 , H04L12/4637 , H04L45/04 , H04L49/107 , H04L49/309 , G06F12/126 , G06F2212/272 , H04L2012/5681
摘要： An improved digital packet switching apparatus enabling enhanced packet transmission and high bandwidth packet transfer. The digital packet switching methods and apparatus permit selectively switching digital signal packet between a set of nodes. The invention includes multiple processing cells, each having a processor coupled to an associated content-addressable memory element. Packet processors, electrically coupled to the memory elements, selectively receive packets from the nodes and transmit the packets into at least one of the plural memory elements; or receive packets from the memory elements and transmit the packets to at least one of the nodes.
摘要翻译：一种改进的数字分组交换装置，其实现增强的分组传输和高带宽分组传输。数字分组交换方法和装置允许在一组节点之间选择性地切换数字信号分组。本发明包括多个处理单元，每个处理单元具有耦合到相关联的内容寻址存储元件的处理器。电耦合到存储器元件的分组处理器选择性地从节点接收分组，并将分组发送到多个存储器元件中的至少一个; 或从存储器元件接收分组，并将分组发送到至少一个节点。

9. 发明授权

US5282201A Dynamic packet routing network 失效
标题翻译：动态分组路由网络
公开(公告)号：US5282201A
公开(公告)日：1994-01-25
申请号：US521798
申请日：1990-05-10
申请人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , David I. Epstein , Stephen W. Morss , Dana R. Kelly , Paul A. Binder
发明人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , David I. Epstein , Stephen W. Morss , Dana R. Kelly , Paul A. Binder
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , H04L12/46 , H04L12/56
CPC分类号： H04L12/5601 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0772 , G06F12/0811 , G06F12/0817 , G06F12/10 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3865 , G06F9/468 , G06F9/5016 , G06F9/52 , H04L12/4637 , H04L45/04 , H04L49/107 , H04L49/255 , H04L49/256 , G06F12/126 , G06F2212/272
摘要： A digital data communications apparatus includes first and second processing groups, each made up of a plurality of processing cells interconnected by an associated bus. An element (RRC) transfers information packets generated by the processing cells between the first and second processing groups. The RRC includes an input for receiving packets from the bus of the first processing group, as well as first and second outputs for outputting packets to the buses of the first and second groups, respectively. A control element routes packets received at the input to a selected one of the outputs based upon a prior history of routings of the datum referenced in that information packet (or requests for that data) between said first and second processing groups.
摘要翻译：数字数据通信装置包括第一和第二处理组，每个处理组由多个由相关总线互连的处理单元组成。元素（RRC）在第一和第二处理组之间传送由处理单元产生的信息分组。 RRC包括用于从第一处理组的总线接收分组的输入，以及用于分别向第一组和第二组的总线输出分组的第一和第二输出。控制元件基于在所述第一和第二处理组之间的该信息分组（或对该数据的请求）中引用的数据的路由的先前历史来将在输入处接收到的分组路由到所选择的一个输出。

10. 发明授权

US5226039A Packet routing switch 失效
标题翻译：分组路由交换机
公开(公告)号：US5226039A
公开(公告)日：1993-07-06
申请号：US526396
申请日：1990-05-18
申请人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , David I. Epstein , Stephen W. Morss , Dana R. Kelly , Paul A. Binder
发明人： Steven J. Frank , Henry Burkhardt, III , James B. Rothnie , David I. Epstein , Stephen W. Morss , Dana R. Kelly , Paul A. Binder
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F11/00 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/12 , G06F15/173 , H04L12/433 , H04L12/46 , H04L12/56
CPC分类号： G06F9/3865 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0772 , G06F12/0811 , G06F12/0817 , G06F12/10 , G06F15/17337 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/468 , G06F9/5016 , G06F9/52 , H04L12/433 , H04L12/4637 , H04L12/5601 , H04L45/00 , H04L45/04 , H04L49/107 , H04L49/256 , G06F12/126 , G06F2212/272 , H04L2012/5605 , H04L2012/562
摘要： A switch is provided for selectively routing digital information packets received from at least first and second external sources to at least first and second external destinations. At least one of the first sources generates an information packet including a datum, or a request therefore, and a corresponding descriptor. First and second routing interconnects have inputs for receiving packets from respective sources and outputs for transmitting packets to respective destinations. The interconnects are also coupled for transferring packets between one another. Directories within the interconnects store descriptors corresponding to data associated with the first destination, as well as requests routed from the other interconnect. A controller routes packets based on the correspondence, or lack thereof, between the descriptor in that packet and an entry signal allocated to corresponding directory.
摘要翻译：提供了一种开关，用于选择性地将从至少第一和第二外部源接收的数字信息分组路由到至少第一和第二外部目的地。第一源中的至少一个源产生包括数据或因此的请求的信息分组和相应的描述符。第一和第二路由互连具有用于从各个源接收分组的输入和用于将分组发送到相应目的地的输出。互连还被耦合用于在彼此之间传送分组。互连中的目录存储对应于与第一目的地相关联的数据的描述符，以及从另一互连路由的请求。控制器基于该分组中的描述符与分配给相应目录的输入信号之间的对应关系或缺乏路由分组。

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