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1. 发明授权

US5341330A Method for writing to a flash memory array during erase suspend intervals 失效
标题翻译：在擦除暂停间隔期间写入闪存阵列的方法
公开(公告)号：US5341330A
公开(公告)日：1994-08-23
申请号：US145732
申请日：1993-11-01
申请人： Steven E. Wells , Mark Winston , Virgil N. Kynett
发明人： Steven E. Wells , Mark Winston , Virgil N. Kynett
IPC分类号： G06F3/06 , G11C16/10 , G11C13/00
CPC分类号： G06F3/0601 , G11C16/102 , G06F2003/0694 , G06F2212/2022
摘要： A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.
摘要翻译：在数据的该部分被擦除和写入的时段期间，将数据写入快闪EEPROM存储器阵列的一部分中的条目的方法被禁止。该方法包括将数据写入除了正被擦除的阵列的部分之外的新的入口位置以及比阵列的原始部分中的原始数据的修订版本号大的修订版本号，写入忙原始条目到除了被擦除的阵列的部分之外的临时存储位置的条件，以及当擦除操作结束时使临时存储位置中列出的条目无效。

2. 发明授权

US5603036A Power management system for components used in battery powered applications 失效
公开(公告)号：US5603036A
公开(公告)日：1997-02-11
申请号：US19617
申请日：1993-02-19
申请人： Steven E. Wells , Virgil N. Kynett , Terry L. Kendall , Richard Garner
发明人： Steven E. Wells , Virgil N. Kynett , Terry L. Kendall , Richard Garner
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/3225 , G06F1/04 , G06F1/3203 , G06F1/3268 , G06F1/3275 , Y02B60/1217 , Y02B60/1228 , Y02B60/1246
摘要： A control circuit for a computer component circuit which includes oscillator apparatus for providing square wave pulses at a prescribed frequency, gating apparatus for providing the square wave pulses at an output terminal for use as a clock for the component circuit, timing apparatus for sensing a period during which the component circuit has not performed an operation, and apparatus for disabling the gating apparatus for providing the square wave pulses at an output terminal.

3. 发明授权

US5249158A Flash memory blocking architecture 失效
标题翻译：闪存阻塞架构
公开(公告)号：US5249158A
公开(公告)日：1993-09-28
申请号：US654263
申请日：1991-02-11
申请人： Virgil N. Kynett , Mickey L. Fandrich , Steven E. Wells , Kurt B. Robinson , Owen W. Jungroth
发明人： Virgil N. Kynett , Mickey L. Fandrich , Steven E. Wells , Kurt B. Robinson , Owen W. Jungroth
IPC分类号： G11C17/00 , G11C8/12 , G11C16/04 , G11C16/06
CPC分类号： G11C8/12 , G11C16/0416
摘要： A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.
摘要翻译：公开了一种用于非易失性半导体存储器中的阻塞结构。这种架构最大限度地减少信号线所占用的器件面积，同时最大化器件产量。此外，该架构最大限度地减少了Y解码机制，同时最大化了设备性能。

4. 发明授权

US5222046A Processor controlled command port architecture for flash memory 失效
标题翻译：闪存的处理器控制命令端口架构
公开(公告)号：US5222046A
公开(公告)日：1993-06-22
申请号：US601012
申请日：1990-10-19
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C16/16 , G11C16/32
CPC分类号： G11C16/16 , G11C16/32
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.
摘要翻译：一种半导体闪存EPROM / EEPROM器件，其包括命令端口控制器，用于从耦合到存储器件的数据总线接收命令指令。命令端口控制器的指令字用于指示设备执行读取，擦除，编程或验证功能，并且命令端口控制器产生必要的控制信号以使存储器正常工作。通过利用命令端口控制器，存储器件可以在器件在电路中被擦除和编程，并允许引脚与现有技术的EPROM和EEPROM兼容。

5. 发明授权

US5053990A Program/erase selection for flash memory 失效
标题翻译： FLASH存储器的程序/擦除选择
公开(公告)号：US5053990A
公开(公告)日：1991-10-01
申请号：US157361
申请日：1988-02-17
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C17/00 , G06F12/00 , G11C16/02 , G11C16/10 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3459
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
摘要翻译：一种半导体闪存EPROM / EEPROM器件，包括用于在数据线上接收指令并向存储器提供控制信号以提供编程和擦除功能的命令端口，编程和擦除存储器的方法。程序序列包括在第一写周期期间设置程序命令，执行第二写周期以将地址寄存器加载到地址寄存器和数据到数据寄存器，在程序周期期间进行编程以及在第三写入期间写入程序验证命令写周期以在读周期中验证编程数据。擦除序列包括在第一写周期期间写入建立擦除命令，在擦除周期期间提供擦除的第二写周期期间的擦除命令，在第三写周期期间写入擦除验证命令，该第三写周期还解决存储器并在读周期期间提供擦除验证。擦除和编程周期都提供测量的增量擦除和编程。

6. 发明授权

US5513136A Nonvolatile memory with blocks and circuitry for selectively protecting the blocks for memory operations 失效
标题翻译：具有用于选择性地保护块以用于存储器操作的块和电路的非易失性存储器
公开(公告)号：US5513136A
公开(公告)日：1996-04-30
申请号：US358978
申请日：1994-12-19
申请人： Mickey L. Fandrich , Virgil N. Kynett , Salim B. Fedel , Thomas C. Price
发明人： Mickey L. Fandrich , Virgil N. Kynett , Salim B. Fedel , Thomas C. Price
IPC分类号： G11C7/24 , G11C16/22 , G11C16/06
CPC分类号： G11C7/24 , G11C16/22
摘要： A nonvolatile memory comprises a memory array and a control circuit coupled to the memory array for performing memory operations with respect to the memory array. A storage circuit associated with the memory array is provided for storing a data. When the data is stored in the storage circuit, the memory array is locked from being accessed for the memory operations. A logic circuit is coupled to the control circuit and the storage circuit for preventing the control circuit from accessing the memory array with respect to the memory operations in accordance with the data. The logic circuit prevents the control circuit from accessing the memory array when the storage circuit stores the data. A control input is provided for receiving a control signal. The control signal is applied to the logic circuit and can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the logic circuit is enabled to lock the memory array with respect to the memory operations in accordance with the data stored in the storage circuit. When the control signal is in the second voltage state, the logic circuit is disabled to lock the memory array and the memory array is allowed for the memory operations regardless of the data stored in the storage circuit.
摘要翻译：非易失性存储器包括存储器阵列和耦合到存储器阵列的控制电路，用于执行存储器阵列的存储器操作。提供与存储器阵列相关联的存储电路用于存储数据。当数据存储在存储电路中时，存储器阵列被锁定以进行存储器操作。逻辑电路耦合到控制电路和存储电路，用于根据数据防止控制电路相对于存储器操作访问存储器阵列。当存储电路存储数据时，逻辑电路防止控制电路访问存储器阵列。提供控制输入用于接收控制信号。控制信号被施加到逻辑电路并且可以处于第一电压状态和第二电压状态。当控制信号处于第一电压状态时，逻辑电路能够根据存储在存储电路中的数据相对于存储器操作锁定存储器阵列。当控制信号处于第二电压状态时，无论存储在存储电路中的数据如何，逻辑电路被禁用以锁定存储器阵列，并且存储器阵列被允许用于存储器操作。

7. 发明授权

US5448712A Circuitry and method for programming and erasing a non-volatile semiconductor memory 失效
标题翻译：用于编程和擦除非易失性半导体存储器的电路和方法
公开(公告)号：US5448712A
公开(公告)日：1995-09-05
申请号：US201044
申请日：1994-02-24
申请人： Virgil N. Kynett , Mickey L. Fandrich
发明人： Virgil N. Kynett , Mickey L. Fandrich
IPC分类号： G11C17/00 , G06F12/00 , G11C16/02 , G11C16/10 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3445 , G11C16/102 , G11C16/3436 , G11C16/3459
摘要： Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state. The erase verification circuitry verifies the erasure of the flash memory array on a byte by byte basis. If the byte currently being verified has been erased; the erase verification circuitry brings a match signal to an active level. The erase control circuitry determines whether additional erase pulses should be applied to the flash array based upon the match signal and the number of erase pulses previously applied to the flash array described is program control circuitry and methods of programming and erasing a flash memory array in response to two step command sequences.
摘要翻译：擦除控制电路以擦除闪存阵列。擦除控制电路与命令状态机一起位于与闪存阵列相同的衬底上。命令状态机识别并向外部产生的擦除命令，并产生一个有效的擦除控制信号，擦除控制电路对其进行响应。擦除控制电路包括预处理脉冲应用电路，擦除脉冲应用电路和擦除验证电路。预处理脉冲应用电路通过将闪速存储器中的每个位编程为表示编程状态的阈值电压电平来预先调整阵列。擦除脉冲施加电路通过将阵列中的每个单元的阈值电压电平提升到表示擦除状态的电平，将一次擦除脉冲一次施加到闪存阵列以擦除闪存阵列。擦除验证电路以逐个字节为基础来验证闪速存储器阵列的擦除。如果当前正在验证的字节已被擦除; 擦除验证电路将匹配信号带到活动电平。擦除控制电路基于匹配信号确定是否应该向闪存阵列施加额外的擦除脉冲，并且先前施加到所述闪存阵列的擦除脉冲的数量是程序控制电路以及响应于编程和擦除闪存阵列的方法到两步命令序列。

8. 发明授权

US5850509A Circuitry for propagating test mode signals associated with a memory array 失效
标题翻译：用于传播与存储器阵列相关联的测试模式信号的电路
公开(公告)号：US5850509A
公开(公告)日：1998-12-15
申请号：US778182
申请日：1997-01-02
申请人： Mickey L. Fandrich , Jerry A. Kreifels , Virgil N. Kynett
发明人： Mickey L. Fandrich , Jerry A. Kreifels , Virgil N. Kynett
IPC分类号： G11C29/12 , G11C29/14 , G06F11/00 , G11C29/00
CPC分类号： G11C29/12 , G11C29/14
摘要： Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.
摘要翻译：用于传播与包括用于存储测试模式信号的多个电路的存储器阵列相关联的测试模式信号的电路，用于选择性地向每个用于存储测试模式信号的电路提供测试模式数据的设备，以及用于同时激活所有电路的设备存储测试模式信号以提供要用于测试的输出信号。

9. 发明授权

US5224070A Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory 失效
标题翻译：用于确定与闪存EEPROM存储器一起使用的编程电路条件的装置
公开(公告)号：US5224070A
公开(公告)日：1993-06-29
申请号：US804965
申请日：1991-12-11
申请人： Mickey L. Fandrich , Virgil N. Kynett , Kurt Robinson
发明人： Mickey L. Fandrich , Virgil N. Kynett , Kurt Robinson
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/34 , G11C29/44 , G11C29/52 , H01L21/822 , H01L27/04
CPC分类号： G11C16/10 , G11C16/3436 , G11C29/44 , G11C29/52 , G11C2216/20
摘要： A circuit which monitors the internal state of flash memory array programming circuitry and conveys that state to circuitry external to the flash memory array so that external circuitry need not delay during any period in which a programming operation is taking place within the flash memory array.
摘要翻译：监视闪存阵列编程电路的内部状态并将该状态传送到闪速存储器阵列外部的电路的电路，使得外部电路不需要在闪存阵列内发生编程操作的任何周期期间延迟。

10. 发明授权

US5197034A Floating gate non-volatile memory with deep power down and write lock-out 失效
标题翻译：浮动门非易失性存储器具有深度断电和写锁定功能
公开(公告)号：US5197034A
公开(公告)日：1993-03-23
申请号：US773247
申请日：1991-10-09
申请人： Mickey Lee Fandrich , Virgil N. Kynett , Kurt B. Robinson
发明人： Mickey Lee Fandrich , Virgil N. Kynett , Kurt B. Robinson
IPC分类号： G11C16/16 , G11C16/30
CPC分类号： G11C16/30 , G11C16/16
摘要： A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.
摘要翻译：描述非易失性存储器。存储器包括包括主块和引导块的存储器阵列。存储器还包括用于接收控制信号的控制输入。控制信号可以处于第一电压状态，第二电压状态和第三电压状态。电路装置被耦合以在控制输入处接收控制信号，用于（1）当控制信号处于第一状态时允许引导块被更新，并且（2）产生电源关闭信号以将存储器切换到基本上当控制信号处于第三电压状态时，断电状态。还描述了一种控制非易失性存储器的方法。

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