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1. 发明授权

US5197034A Floating gate non-volatile memory with deep power down and write lock-out 失效
标题翻译：浮动门非易失性存储器具有深度断电和写锁定功能
公开(公告)号：US5197034A
公开(公告)日：1993-03-23
申请号：US773247
申请日：1991-10-09
申请人： Mickey Lee Fandrich , Virgil N. Kynett , Kurt B. Robinson
发明人： Mickey Lee Fandrich , Virgil N. Kynett , Kurt B. Robinson
IPC分类号： G11C16/16 , G11C16/30
CPC分类号： G11C16/30 , G11C16/16
摘要： A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.
摘要翻译：描述非易失性存储器。存储器包括包括主块和引导块的存储器阵列。存储器还包括用于接收控制信号的控制输入。控制信号可以处于第一电压状态，第二电压状态和第三电压状态。电路装置被耦合以在控制输入处接收控制信号，用于（1）当控制信号处于第一状态时允许引导块被更新，并且（2）产生电源关闭信号以将存储器切换到基本上当控制信号处于第三电压状态时，断电状态。还描述了一种控制非易失性存储器的方法。

2. 发明授权

US5463757A Command interface between user commands and a memory device 失效
标题翻译：用户命令和存储设备之间的命令界面
公开(公告)号：US5463757A
公开(公告)日：1995-10-31
申请号：US185449
申请日：1994-01-21
申请人： Mickey L. Fandrich , Kelvin W. Lee , Jerry A. Kreiffels , Virgil N. Kynett , Kurt B. Robinson
发明人： Mickey L. Fandrich , Kelvin W. Lee , Jerry A. Kreiffels , Virgil N. Kynett , Kurt B. Robinson
IPC分类号： G06F12/14 , G11C16/02 , G11C16/10 , G11C16/32 , G11C17/00 , G06F12/00
CPC分类号： G11C16/32 , G11C16/10 , G11C2216/20
摘要： A command state machine for control circuitry associated with a memory array which control circuitry includes apparatus for programming and erasing the memory array including first state machine logic apparatus for providing control signals for reading the memory array and for initiating operations of the apparatus for programming and erasing the memory array in response to commands, and second state machine logic apparatus for controlling information derived from the memory array, the first and second state machine logic apparatus being adapted to assume predetermined states in response to any invalid command which have no adverse affect on the memory array or the control circuitry.
摘要翻译：一种用于与存储器阵列相关联的控制电路的命令状态机，所述控制电路包括用于编程和擦除存储器阵列的装置，所述装置包括用于提供用于读取存储器阵列的控制信号的第一状态机逻辑装置，以及用于启动用于编程和擦除的装置的操作所述存储器阵列响应于命令，以及用于控制从所述存储器阵列导出的信息的第二状态机逻辑装置，所述第一和第二状态机逻辑装置适于响应于对所述存储阵列没有不利影响的任何无效命令而呈现预定状态存储器阵列或控制电路。

3. 发明授权

US5249158A Flash memory blocking architecture 失效
标题翻译：闪存阻塞架构
公开(公告)号：US5249158A
公开(公告)日：1993-09-28
申请号：US654263
申请日：1991-02-11
申请人： Virgil N. Kynett , Mickey L. Fandrich , Steven E. Wells , Kurt B. Robinson , Owen W. Jungroth
发明人： Virgil N. Kynett , Mickey L. Fandrich , Steven E. Wells , Kurt B. Robinson , Owen W. Jungroth
IPC分类号： G11C17/00 , G11C8/12 , G11C16/04 , G11C16/06
CPC分类号： G11C8/12 , G11C16/0416
摘要： A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.
摘要翻译：公开了一种用于非易失性半导体存储器中的阻塞结构。这种架构最大限度地减少信号线所占用的器件面积，同时最大化器件产量。此外，该架构最大限度地减少了Y解码机制，同时最大化了设备性能。

4. 发明授权

US07327370B2 Memory controller hub interface 有权
标题翻译：内存控制器集线器接口
公开(公告)号：US07327370B2
公开(公告)日：2008-02-05
申请号：US11174662
申请日：2005-07-06
申请人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
发明人： Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
IPC分类号： G06F13/14 , G06F15/16
CPC分类号： G06F3/14 , G06T1/20 , G09G5/001
摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译：存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。

5. 发明授权

US5544356A Block-erasable non-volatile semiconductor memory which tracks and stores the total number of write/erase cycles for each block 失效
标题翻译：块可擦除非易失性半导体存储器，其跟踪并存储每个块的写入/擦除周期的总数
公开(公告)号：US5544356A
公开(公告)日：1996-08-06
申请号：US400272
申请日：1995-03-03
申请人： Kurt B. Robinson , Dale K. Elbert , Markus A. Levy
发明人： Kurt B. Robinson , Dale K. Elbert , Markus A. Levy
IPC分类号： G06F3/06 , G06F12/00 , G06F12/02 , G06F12/06 , G11C16/02 , G11C16/34 , G06F17/30
CPC分类号： G06F3/0601 , G06F12/023 , G06F12/0246 , G06F12/0638 , G11C16/349 , G06F2003/0694 , G06F2212/7211 , Y10S707/99956 , Y10S707/99957
摘要： A non-volatile semiconductor memory that is erasable only in blocks is described. Each bit of the non-volatile semiconductor memory cannot be overwritten from a first logical state to a second logical state without a prior erasure. Each bit of the non-volatile semiconductor memory can be overwritten from a second logical state to a first logical state without a prior erasure. The non-volatile semiconductor memory comprises an active block for storing a first file, a reserve block for storing a second file, and a directory block. The second file is a copy of the first file. The copy is made during a clean-up operation prior to erasure of the active block. The directory block comprises a directory entry for identifying the first file.
摘要翻译：描述了仅在块中可擦除的非易失性半导体存储器。不存在先前的擦除，非易失性半导体存储器的每一位都不能被从第一逻辑状态重写到第二逻辑状态。可以将非易失性半导体存储器的每一位从第二逻辑状态重写到第一逻辑状态，而无需先前擦除。非易失性半导体存储器包括用于存储第一文件的活动块，用于存储第二文件的预留块和目录块。第二个文件是第一个文件的副本。在擦除活动块之前，在清理操作期间进行复印。目录块包括用于识别第一文件的目录条目。

6. 发明授权

US5388248A Flash memory card including plural flash memories and circuitry for selectively outputting ready/busy signals in different operating modes 失效
标题翻译：闪存卡包括多个闪存和用于在不同操作模式下选择性地输出就绪/忙信号的电路
公开(公告)号：US5388248A
公开(公告)日：1995-02-07
申请号：US198789
申请日：1994-02-16
申请人： Kurt B. Robinson , Russell D. Eslick , Markus A. Levy , David M. Brown , Lily C. Pao , Brian L. Dipert
发明人： Kurt B. Robinson , Russell D. Eslick , Markus A. Levy , David M. Brown , Lily C. Pao , Brian L. Dipert
IPC分类号： G06F12/06 , G06F12/00 , G06K19/07 , G11C5/00 , G11C16/02 , G11C16/10 , G11C17/00 , G06F13/00 , G06K19/067 , G11C16/06
CPC分类号： G11C16/10 , G11C16/102
摘要： A flash memory card is described which has a plurality of flash memories, each having a ready/busy output for indicating whether its respective one of the plurality of flash memories is busy or ready. A register circuit is provided for storing a plurality of mask data. A mode circuit is provided for choosing one of a first mode and a second mode, wherein a first mode signal is produced if the first mode is chosen and a second mode signal is produced if the second mode is chosen. A logic circuit is provided for performing logical operations with respect to the ready/busy output for each of the plurality of flash memories and the mask data in accordance with whether the first mode signal or the second mode signal is produced. If the first mode is chosen, the logic circuit produces a ready signal output for the flash memory card only if the ready/busy output of all the plurality of flash memories is ready. If the second mode is chosen, the logic circuit produces a ready signal output for the flash memory card each time any flash memory goes from being busy to being ready.
摘要翻译：描述了一种闪存卡，其具有多个闪速存储器，每个闪速存储器具有用于指示其相应的一个闪存是忙还是准备好的就绪/忙输出。提供了一种用于存储多个掩模数据的寄存器电路。提供了用于选择第一模式和第二模式之一的模式电路，其中如果选择了第一模式，则产生第一模式信号，并且如果选择了第二模式，则产生第二模式信号。提供逻辑电路，用于根据是否产生第一模式信号或第二模式信号，针对多个闪速存储器中的每一个和掩模数据执行关于就绪/忙输出的逻辑运算。如果选择第一模式，则只有当所有多个闪存的就绪/忙输出准备就绪时，逻辑电路才会为闪存卡产生就绪信号输出。如果选择第二模式，则每当闪存从忙到准备状态时，逻辑电路就为闪存卡产生就绪信号输出。

7. 发明授权

US09761131B2 Systems and methods involving features of adaptive and/or autonomous traffic control 有权
公开(公告)号：US09761131B2
公开(公告)日：2017-09-12
申请号：US14474232
申请日：2014-09-01
申请人： Kurt B. Robinson
发明人： Kurt B. Robinson
IPC分类号： G06F19/00 , G06G7/70 , G06G7/76 , G08G1/00 , G08G1/01 , G08G1/042 , G06K9/00
CPC分类号： G08G1/0116 , G06K9/00785 , G08G1/0145 , G08G1/042
摘要： Systems and method are disclosed for adaptive and/or autonomous traffic control. In one illustrative implementation, there is provided a method for processing traffic information. Moreover, the method may include receiving data regarding travel of vehicles associated with an intersection, using neural network technology to recognize types and/or states of traffic, and using the neural network technology to process/determine/memorize optimal traffic flow decisions as a function of experience information. Exemplary implementations may also include using the neural network technology to achieve efficient traffic flow via recognition of the optimal traffic flow decisions.

8. 发明授权

US06279069B1 Interface for flash EEPROM memory arrays 失效
标题翻译：闪存EEPROM存储器阵列接口
公开(公告)号：US06279069B1
公开(公告)日：2001-08-21
申请号：US08773169
申请日：1996-12-26
申请人： Kurt B. Robinson , Mark Christopherson , Terry Kendall
发明人： Kurt B. Robinson , Mark Christopherson , Terry Kendall
IPC分类号： G06F1200
CPC分类号： G11C16/06 , G11C16/20
摘要： A flash EEPROM memory device including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash memory device that may be used to initialize software device drivers for accessing the device, and an interface for receiving data and commands addressed to the blocks of flash EEPROM memory cells and generating signals for affecting the purpose of the commands in the flash EEPROM memory device, the interface adapted to receive a command scaled to a range of characteristics of a particular flash EEPROM memory device and respond by returning the data stored in the query memory as output depending on characteristics of the particular flash EEPROM memory device.
摘要翻译：一种闪存EEPROM存储器件，包括布置成以行和列进行访问的多个快闪EEPROM存储器单元块;查询存储器，存储定义可用于初始化软件设备驱动程序以访问设备的闪速存储器件的特性的数据; 以及接口，用于接收寻址到快闪EEPROM存储器单元的块的数据和命令，并且产生用于影响闪存EEPROM存储器件中的命令的目的的信号，该接口适于接收缩放到特定范围的特征范围的命令闪存EEPROM存储器件，并根据特定的闪存EEPROM存储器件的特性返回存储在查询存储器中的数据作为输出。

9. 发明授权

US5532945A Power budgetting in a computer system having removable devices 失效
标题翻译：具有可移动设备的计算机系统中的功率预算
公开(公告)号：US5532945A
公开(公告)日：1996-07-02
申请号：US261447
申请日：1994-06-17
申请人： Kurt B. Robinson
发明人： Kurt B. Robinson
IPC分类号： G06F1/32 , G11C5/14 , G06F1/00 , G11C7/00
CPC分类号： G06F1/3215 , G11C5/14
摘要： A computer system with power budgeting for removable devices is disclosed comprising a nonvolatile memory that contains a power resource table for storing a power consumption indication for at least one resident device for the computer system. The computer system further comprises a removable device that contains a card information structure that stores a power consumption indication for the removable device. A processor executes a power management driver that allocates a power budget to the removable device according to the power resource table and the card information structure. The power management driver updates the power: resource table to indicate the power budget to the removable device.
摘要翻译：公开了一种具有用于可移动设备的功率预算的计算机系统，包括：非易失性存储器，其包含用于存储用于所述计算机系统的至少一个驻留设备的功率消耗指示的功率资源表。计算机系统还包括可移动设备，其包含存储可移除设备的功耗指示的卡信息结构。处理器执行功率管理驱动器，其根据功率资源表和卡信息结构向可移动设备分配功率预算。电源管理驱动程序更新power：资源表以指示可移动设备的功率预算。

10. 发明授权

US5379401A Flash memory card including circuitry for selectively providing masked and unmasked ready/busy output signals 失效
标题翻译：闪存卡包括用于选择性地提供屏蔽和未屏蔽的就绪/忙碌输出信号的电路
公开(公告)号：US5379401A
公开(公告)日：1995-01-03
申请号：US198134
申请日：1994-02-16
申请人： Kurt B. Robinson , Russell D. Eslick , Markus A. Levy , David M. Brown , Lily C. Pao , Brian L. Dipert
发明人： Kurt B. Robinson , Russell D. Eslick , Markus A. Levy , David M. Brown , Lily C. Pao , Brian L. Dipert
IPC分类号： G06F12/06 , G06F12/00 , G06K19/07 , G11C5/00 , G11C16/02 , G11C16/10 , G11C17/00 , G06F13/00 , G06K19/067 , G11C16/06
CPC分类号： G11C16/10 , G11C16/102
摘要： A flash memory card is described which includes a first flash memory and a second flash memory. The first flash memory includes an unmasked first output that enters a first state if the first flash memory is ready and a second state if the first flash memory is busy. The second flash memory includes an unmasked second output that enters the first state if the second flash memory is ready and the second state if the second flash memory is busy. The flash memory card also includes a circuit for selectively providing one of (1) a masked first output (2) the unmasked first output, (3) a masked second output, and (4) the unmasked second output. A latch provides a first ready output signal for the flash memory card. The first ready output signal indicates a first transition from the second state to the first state by one of the unmasked first output of the first flash memory and the unmasked second output of the second flash memory. A circuit is also provided for clearing the first ready output signal from the latch.
摘要翻译：描述了包括第一闪存和第二闪存的闪存卡。第一闪速存储器包括未屏蔽的第一输出，如果第一闪速存储器就绪，则进入第一状态，如果第一闪存正忙，则其进入第二状态。第二闪速存储器包括未屏蔽的第二输出，如果第二闪速存储器准备就进入第一状态，如果第二闪速存储器正忙，则其进入第二状态。闪存卡还包括用于选择性地提供（1）屏蔽的第一输出（2）未屏蔽的第一输出，（3）屏蔽的第二输出和（4）未屏蔽的第二输出之一的电路。锁存器为闪存卡提供第一个就绪输出信号。第一准备输出信号指示第一闪速存储器的未屏蔽的第一输出和第二闪存的未屏蔽的第二输出之一从第二状态到第一状态的第一转换。还提供用于清除来自锁存器的第一就绪输出信号的电路。

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