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1. 发明申请

US20120096226A1 TWO LEVEL REPLACEMENT SCHEME OPTIMIZES FOR PERFORMANCE, POWER, AND AREA 审中-公开
标题翻译：两级替代方案优化性能，功率和面积
公开(公告)号：US20120096226A1
公开(公告)日：2012-04-19
申请号：US12906936
申请日：2010-10-18
申请人： Stephen P. Thompson , Robert Krick , Tarun Nakra
发明人： Stephen P. Thompson , Robert Krick , Tarun Nakra
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/121 , Y02D10/13
摘要： A two-level replacement scheme is provided for selecting an entry in a cache memory to replace when a cache miss takes place and the memory is full. The scheme divides the tags associated with each memory location of the cache into two or more groups, each group relating to a subset of memory locations of the cache. The scheme uses a first algorithm to select one of the groups and passes the tags for the group through a second algorithm. The second algorithm produces a local index which, when combined with a group index, produces a replacement index that identifies a memory location in the cache to replace.
摘要翻译：提供两级替换方案，用于选择高速缓冲存储器中的条目以替代发生高速缓存未命中并且存储器已满。该方案将与高速缓存的每个存储器位置相关联的标签划分成两个或更多个组，每个组涉及高速缓存的存储器位置的子集。该方案使用第一种算法来选择一个组，并通过第二种算法传递该组的标签。第二种算法产生本地索引，当与组索引组合时，产生一个替换索引，该索引标识要替换的高速缓存中的内存位置。

2. 发明授权

US09058269B2 Method and apparatus including a probe filter for shared caches utilizing inclusion bits and a victim probe bit 有权
标题翻译：包括用于使用包含位的共享高速缓存的探测过滤器和受害者探针位的方法和装置
公开(公告)号：US09058269B2
公开(公告)日：2015-06-16
申请号：US13532009
申请日：2012-06-25
申请人： Robert Krick , John M. King , Tarun Nakra
发明人： Robert Krick , John M. King , Tarun Nakra
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/084 , G06F2212/62 , G06F2212/621
摘要： A method and apparatus use one or more inclusion bits and a victim bit to filter probes to shared caches. One embodiment of the method includes filtering a probe or snoop of one or more of a plurality of first caches based on a plurality of first bits, such as inclusion bits, associated with a line indicated by the probe or snoop. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit, such as a victim probe bit, indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. The first caches may be L1 caches and the first bits may be stored in an L2 cache of a multilevel cache.
摘要翻译：方法和装置使用一个或多个包含比特和受害者比特来将探测过滤到共享高速缓存。该方法的一个实施例包括基于与由探测器或窥探指示的线相关联的多个第一比特（例如包含比特）来过滤多个第一高速缓存中的一个或多个的探测或窥探。多个第一比特中的每一个与多个第一高速缓存的不同子集相关联，并且每个第一比特指示线是否驻留在多个第一高速缓存的相应子集中。诸如受害者探测位的第二位指示在多个第一高速缓存的至少一个子集中该行是否驻留在多个第一高速缓存中的多于一个中。第一高速缓存可以是L1高速缓存，并且第一位可以存储在多级缓存的L2高速缓存中。

3. 发明授权

US07856633B1 LRU cache replacement for a partitioned set associative cache 有权
标题翻译：用于分区集关联高速缓存的LRU缓存替换
公开(公告)号：US07856633B1
公开(公告)日：2010-12-21
申请号：US09534191
申请日：2000-03-24
申请人： Chan W. Lee , Glenn Hinton , Robert Krick
发明人： Chan W. Lee , Glenn Hinton , Robert Krick
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/50 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F12/0842 , G06F12/121
摘要： A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.
摘要翻译：分割与多线程处理器相关联的存储器资源的方法包括定义存储器资源以分别包括专用于第一和第二线程的第一和第二部分。然后，内存资源的第三部分被指定为在第一和第二线程之间共享。在接收到信息项目（例如，与第一线程相关并且要存储在存储器资源中的微指令）时，检查最近最少使用（LRU）部分的历史以识别在第一或第三部分，而不是第二部分，作为最近最少使用的部分。第二部分由于专用于第二线程而被排除在本次考试之外。然后将信息项目存储在第一或第三部分内，被标识为最近最少使用的位置内。

4. 发明申请

US20120079350A1 METHOD AND APPARATUS FOR CALCULATING ERROR CORRECTION CODES FOR SELECTIVE DATA UPDATES 有权
标题翻译：用于选择性数据更新的计算错误校正码的方法和装置
公开(公告)号：US20120079350A1
公开(公告)日：2012-03-29
申请号：US12893501
申请日：2010-09-29
申请人： Robert Krick
发明人： Robert Krick
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/05 , H03M13/093 , H03M13/611
摘要： The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error correction code bits formed from a plurality of data bits in response to changes in a first subset of the data bits. The first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits.
摘要翻译：本发明提供一种用于选择性地更新纠错码位的方法和装置。该方法的一个实施例包括响应于数据比特的第一子集中的变化，确定由多个数据比特形成的多个纠错码比特的第一子集。多个纠错码位的第一子集小于多个纠错码位的全部。

5. 发明申请

US20120096295A1 METHOD AND APPARATUS FOR DYNAMIC POWER CONTROL OF CACHE MEMORY 审中-公开
标题翻译：高速缓存存储器动态功率控制的方法与装置
公开(公告)号：US20120096295A1
公开(公告)日：2012-04-19
申请号：US12906472
申请日：2010-10-18
申请人： Robert Krick
发明人： Robert Krick
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F12/0802 , G06F12/0864 , G06F12/0891 , G06F12/0893 , G06F2212/1028 , G06F2212/601 , Y02D10/13 , Y02D10/14
摘要： The present invention provides a method and apparatus for dynamic power control of a cache memory. One embodiment of the method includes disabling a subset of lines in the cache memory to reduce power consumption during operation of the cache memory.
摘要翻译：本发明提供了一种用于高速缓冲存储器的动态功率控制的方法和装置。该方法的一个实施例包括禁用高速缓冲存储器中的线路子集以减少高速缓冲存储器的操作期间的功耗。

6. 发明授权

US5630107A System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy 失效
$System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy$
标题翻译：当总线分数寄存器处于第一或第二状态且总线单元不忙时，用于从总线分数寄存器加载PLL的系统
公开(公告)号：US5630107A
公开(公告)日：1997-05-13
申请号：US210066
申请日：1994-03-16
申请人： Douglas Carmean , Kathakali Debnath , Roshan Fernando , Robert Krick , Keng Wong
发明人： Douglas Carmean , Kathakali Debnath , Roshan Fernando , Robert Krick , Keng Wong
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling. The internal and I/O clocks are signaled to stop in response to a NOP micro instruction placed in the pipe line, that indicates that the pipeline is clear of pending instructions. A number of NOPs are executed, the number being determined by the amount of time required by the I/O clock to stop.
摘要翻译：包括具有编码的总线分数寄存器的微处理器，当被解码时指示总线编码或停止时钟功能，数据处理逻辑包括布置为指令流水线的包括总线单元的多个单元。这些单元由以第一频率运行的内部时钟计时，并且以由第二频率运行的I / O时钟的I / O总线运行，该第二频率是第一频率的一部分。在总线分数寄存器包含停止时钟编码的条件下产生停止时钟信号。轮询总线单元忙（BBSY）信号线以确保流水线中的所有待处理总线周期完成，响应于停止时钟信号启动轮询。运行编码以指示停止时钟功能的特殊周期来通知微处理器的单元内部和I / O时钟将停止切换。响应于放置在管线中的NOP微指令，内部和I / O时钟发出信号停止，表示管道没有待处理的指令。执行多个NOP，该数量由I / O时钟停止所需的时间量决定。

7. 发明授权

US08924817B2 Method and apparatus for calculating error correction codes for selective data updates 有权
标题翻译：用于计算选择性数据更新的纠错码的方法和装置
公开(公告)号：US08924817B2
公开(公告)日：2014-12-30
申请号：US12893501
申请日：2010-09-29
申请人： Robert Krick
发明人： Robert Krick
IPC分类号： G11C29/00 , H03M13/00 , H03M13/05 , G06F11/10 , H03M13/09
CPC分类号： G06F11/1064 , H03M13/05 , H03M13/093 , H03M13/611
摘要： The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error correction code bits formed from a plurality of data bits in response to changes in a first subset of the data bits. The first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits.
摘要翻译：本发明提供一种用于选择性地更新纠错码位的方法和装置。该方法的一个实施例包括响应于数据比特的第一子集中的变化，确定由多个数据比特形成的多个纠错码比特的第一子集。多个纠错码位的第一子集小于多个纠错码位的全部。

8. 发明授权

US08751745B2 Method for concurrent flush of L1 and L2 caches 有权
标题翻译： L1和L2高速缓存的并发冲突方法
公开(公告)号：US08751745B2
公开(公告)日：2014-06-10
申请号：US12854658
申请日：2010-08-11
申请人： Robert Krick , David Kaplan
发明人： Robert Krick , David Kaplan
IPC分类号： G06F12/12
CPC分类号： G06F12/0891
摘要： The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.
摘要翻译：本发明提供了一种与分级缓存系统一起使用的方法和装置。该方法可以包括同时刷新多级高速缓存的一个或多个第一高速缓存和第二高速缓存。与第二级缓存相比，多级缓存中的每个第一高速缓存都较小，处于较低级别。

9. 发明授权

US07149883B1 Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue 有权
标题翻译：方法和装置基于所指示的存储在队列内的指令的有效性或无效性来选择性地提前队列的写指针
公开(公告)号：US07149883B1
公开(公告)日：2006-12-12
申请号：US09539734
申请日：2000-03-30
申请人： Per Hammarlund , Robert Krick
发明人： Per Hammarlund , Robert Krick
IPC分类号： G06F9/00
CPC分类号： G06F9/382 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F9/3851
摘要： A buffer mechanism for buffering microinstructions between a trace cache and an allocator performs a compacting operation by overwriting entries within a queue, known not to store valid instructions or data, with valid instructions or data. Following a write operation to a queue included within the buffer mechanism, pointer logic determines whether the entries to which instructions or data have been written include the valid data or instructions. If an entry is shown to be invalid, the write pointer is not advanced past the relevant entry. In this way, an immediately following write operation will overwrite the invalid data or instruction with data or instruction. The overwriting instruction or data will again be subject to scrutiny (e.g., a qualitative determination) to determine whether it is valid or invalid, and will only be retained within the queue if valid.
摘要翻译：用于缓冲跟踪高速缓存和分配器之间的微指令的缓冲机制通过覆盖队列中已知不存储有效指令或数据的条目与有效指令或数据来执行压缩操作。在对缓冲机制中包括的队列进行写入操作之后，指针逻辑确定是否写入了指令或数据的条目包括有效的数据或指令。如果一个条目显示为无效，则写入指针不会超过相关条目。以这种方式，紧随其后的写操作将用数据或指令覆盖无效数据或指令。覆盖指令或数据将再次受到审查（例如，定性确定），以确定其是有效还是无效，并且只有在有效时才会保留在队列中。

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