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1. 发明授权

US07856633B1 LRU cache replacement for a partitioned set associative cache 有权
标题翻译：用于分区集关联高速缓存的LRU缓存替换
公开(公告)号：US07856633B1
公开(公告)日：2010-12-21
申请号：US09534191
申请日：2000-03-24
申请人： Chan W. Lee , Glenn Hinton , Robert Krick
发明人： Chan W. Lee , Glenn Hinton , Robert Krick
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/50 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F12/0842 , G06F12/121
摘要： A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.
摘要翻译：分割与多线程处理器相关联的存储器资源的方法包括定义存储器资源以分别包括专用于第一和第二线程的第一和第二部分。然后，内存资源的第三部分被指定为在第一和第二线程之间共享。在接收到信息项目（例如，与第一线程相关并且要存储在存储器资源中的微指令）时，检查最近最少使用（LRU）部分的历史以识别在第一或第三部分，而不是第二部分，作为最近最少使用的部分。第二部分由于专用于第二线程而被排除在本次考试之外。然后将信息项目存储在第一或第三部分内，被标识为最近最少使用的位置内。

2. 发明授权

US08219757B2 Apparatus and method for low touch cache management 有权
标题翻译：低触控缓存管理的装置和方法
公开(公告)号：US08219757B2
公开(公告)日：2012-07-10
申请号：US12286460
申请日：2008-09-30
申请人： Glenn Hinton , Dale Juenemann , R. Scott Tetrick
发明人： Glenn Hinton , Dale Juenemann , R. Scott Tetrick
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0888 , G06F2212/1021 , G06F2212/222
摘要： In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，基于处理器的系统包括处理器，耦合到处理器的系统存储器，大容量存储设备，位于系统存储器和大容量存储设备之间的高速缓冲存储器以及存储在基于处理器的系统上的代码使基于处理器的系统利用高速缓冲存储器。代码可以被配置为使得基于处理器的系统优先仅使用所选大小的高速缓冲存储器来存储具有小于或等于所选数量的高速缓存命中的高速缓存条目。公开和要求保护其他实施例。

3. 发明申请

US20120079232A1 APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES 有权
标题翻译：用于实施微型表格的装置，方法和系统
公开(公告)号：US20120079232A1
公开(公告)日：2012-03-29
申请号：US12890585
申请日：2010-09-24
申请人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
发明人： Glenn Hinton , Madhavan Parthasarathy , Rajesh Parthasarathy , Muthukumar Swaminathan , Raj Ramanujan , David Zimmerman , Larry O. Smith , Adrian C. Moga , Scott J. Cape , Wayne A. Downer , Robert S. Chappell
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.
摘要翻译：公开了一种装置，方法，机器可读介质和系统。在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

4. 发明申请

US20080082785A1 Vector completion mask handling 有权
标题翻译：矢量完成掩码处理
公开(公告)号：US20080082785A1
公开(公告)日：2008-04-03
申请号：US11529850
申请日：2006-09-29
申请人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
发明人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
IPC分类号： G06F15/76
CPC分类号： G06F9/3824 , G06F9/30036 , G06F15/8084
摘要： Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.
摘要翻译：提供矢量完成掩码（VCM）处理技术。数据结构包括用于特定操作的每个操作数的掩码字段。处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

5. 发明申请

US20070061558A1 Method and apparatus for quick resumption 有权
标题翻译：快速恢复的方法和装置
公开(公告)号：US20070061558A1
公开(公告)日：2007-03-15
申请号：US11229203
申请日：2005-09-15
申请人： Michael Rothman , Glenn Hinton , Mark Doran , Vincent Zimmer , Michael Kinney
发明人： Michael Rothman , Glenn Hinton , Mark Doran , Vincent Zimmer , Michael Kinney
IPC分类号： G06F9/00
CPC分类号： G06F9/4418
摘要： During a process of transitioning a processing system from sleep mode to active mode, system firmware of the processing system may automatically determine whether an initialization task has been assigned to a component other than system firmware, based on data obtained from a resume descriptor stored in nonvolatile storage of the processing system. The system firmware may skip the initialization task if the initialization task has been assigned to a component other than the system firmware. For example, in one embodiment, the system firmware may determine whether the resume descriptor identifies one or more memory ranges. If so, the system firmware may forego initialization of at least one memory range identified in the resume descriptor when initializing a random access memory (RAM) of the processing system. Other embodiments are described and claimed.
摘要翻译：在将处理系统从睡眠模式转换到活动模式的过程中，处理系统的系统固件可以基于从存储在非易失性存储器中的恢复描述符获得的数据自动地确定初始化任务是否已被分配给系统固件以外的组件存储处理系统。如果将初始化任务分配给系统固件以外的组件，系统固件可能会跳过初始化任务。例如，在一个实施例中，系统固件可以确定恢复描述符是否识别一个或多个存储器范围。如果是这样，当初始化处理系统的随机存取存储器（RAM）时，系统固件可以放弃在恢复描述符中标识的至少一个存储器范围的初始化。描述和要求保护其他实施例。

6. 发明申请

US20130151876A1 METHOD AND APPARATUS FOR QUICK RESUMPTION 有权
标题翻译：快速恢复的方法和装置
公开(公告)号：US20130151876A1
公开(公告)日：2013-06-13
申请号：US13764245
申请日：2013-02-11
申请人： Michael Rothman , Glenn Hinton , Vincent Zimmer , Michael Kinney , Mark Doran
发明人： Michael Rothman , Glenn Hinton , Vincent Zimmer , Michael Kinney , Mark Doran
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.
摘要翻译：当从睡眠模式转换到活动模式时，处理系统将第一级恢复内容和第二级恢复内容加载到处理系统的易失性存储器中。第一阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的第一程序的上下文数据。第二阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的另一程序的上下文数据。处理系统可以在所有第二阶段恢复内容已经被加载到易失性存储器之前为第一程序提供用户界面。描述和要求保护其他实施例。

7. 发明授权

US08171321B2 Method and apparatus for cost and power efficient, scalable operating system independent services 有权
标题翻译：用于成本和功率高效，可扩展的操作系统独立服务的方法和设备
公开(公告)号：US08171321B2
公开(公告)日：2012-05-01
申请号：US11964439
申请日：2007-12-26
申请人： Arvind Kumar , Per Hammarlund , Glenn Hinton , Johan G. Van De Groenendaal
发明人： Arvind Kumar , Per Hammarlund , Glenn Hinton , Johan G. Van De Groenendaal
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3209 , Y02D10/171
摘要： A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.
摘要翻译：提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

8. 发明申请

US20080151648A1 High speed fanned out system architecture and input/output circuits for non-volatile memory 有权
标题翻译：高速扇出系统架构和非易失性存储器的输入/输出电路
公开(公告)号：US20080151648A1
公开(公告)日：2008-06-26
申请号：US11645043
申请日：2006-12-21
申请人： Sean S. Eilert , Rodney R. Rozman , Shekoufeh Qawami , Glenn Hinton
发明人： Sean S. Eilert , Rodney R. Rozman , Shekoufeh Qawami , Glenn Hinton
IPC分类号： G11C7/10
CPC分类号： G06F13/4239 , G11C16/10 , G11C16/26 , G11C2216/14
摘要： In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.
摘要翻译：在各种实施例中，诸如NAND闪存器件的多个非易失性存储器件可以以扇形输出配置连接到主机控制器设备，其允许多个存储器件中的每一个执行读取和/或写入操作同时。每个非易失性存储器件可以包括高速输入电路和高速输出电路，使得到存储器和从存储器的传送不受闪存读/写接口的速度的限制。

9. 发明申请

US20070061556A1 Method and apparatus for quick resumption 有权
标题翻译：快速恢复的方法和装置
公开(公告)号：US20070061556A1
公开(公告)日：2007-03-15
申请号：US11229126
申请日：2005-09-15
申请人： Michael Rothman , Glenn Hinton , Mark Doran , Vincent Zimmer , Michael Kinney
发明人： Michael Rothman , Glenn Hinton , Mark Doran , Vincent Zimmer , Michael Kinney
IPC分类号： G06F9/00
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.
摘要翻译：当从睡眠模式转换到活动模式时，处理系统将第一级恢复内容和第二级恢复内容加载到处理系统的易失性存储器中。第一阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的第一程序的上下文数据。第二阶段恢复内容可以包含在处理系统转换到睡眠模式之前正在使用的另一程序的上下文数据。处理系统可以在所有第二阶段恢复内容已经被加载到易失性存储器之前为第一程序提供用户界面。描述和要求保护其他实施例。

10. 发明授权

US08433854B2 Apparatus and method for cache utilization 有权
公开(公告)号：US08433854B2
公开(公告)日：2013-04-30
申请号：US12215093
申请日：2008-06-25
申请人： R. Scott Tetrick , Dale Juenemann , Jordan Howes , Jeanna Matthews , Steven Wells , Glenn Hinton , Oscar Pinto
发明人： R. Scott Tetrick , Dale Juenemann , Jordan Howes , Jeanna Matthews , Steven Wells , Glenn Hinton , Oscar Pinto
IPC分类号： G06F12/00
CPC分类号： G06F12/0868 , G06F12/0888 , G06F2212/222 , Y02D10/13
摘要： In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

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