专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5630107A System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy 失效
$System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy$
标题翻译：当总线分数寄存器处于第一或第二状态且总线单元不忙时，用于从总线分数寄存器加载PLL的系统
公开(公告)号：US5630107A
公开(公告)日：1997-05-13
申请号：US210066
申请日：1994-03-16
申请人： Douglas Carmean , Kathakali Debnath , Roshan Fernando , Robert Krick , Keng Wong
发明人： Douglas Carmean , Kathakali Debnath , Roshan Fernando , Robert Krick , Keng Wong
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A micro processor including a bus fraction register with an encoding which when decoded indicates either a bus fraction encoding or a stop clock function, data processing logic that includes a number of units including a bus unit, arranged as an instruction pipeline. The units are clocked by an internal clock running at a first frequency and operating with an I/O bus clocked by an I/O clock running at a second frequency which is a fraction of the first frequency. A stop clock signal is generated upon the condition that the bus fraction register contains the stop clock encoding. A bus unit busy (BBSY) signal line is polled to ensure that all pending bus cycles in the pipeline are completed, the polling being initiated in response to the stop clock signal. A special cycle encoded to indicate the stop clock function is run to inform the units of the microprocessor that the internal and I/O clocks are going to stop toggling. The internal and I/O clocks are signaled to stop in response to a NOP micro instruction placed in the pipe line, that indicates that the pipeline is clear of pending instructions. A number of NOPs are executed, the number being determined by the amount of time required by the I/O clock to stop.
摘要翻译：包括具有编码的总线分数寄存器的微处理器，当被解码时指示总线编码或停止时钟功能，数据处理逻辑包括布置为指令流水线的包括总线单元的多个单元。这些单元由以第一频率运行的内部时钟计时，并且以由第二频率运行的I / O时钟的I / O总线运行，该第二频率是第一频率的一部分。在总线分数寄存器包含停止时钟编码的条件下产生停止时钟信号。轮询总线单元忙（BBSY）信号线以确保流水线中的所有待处理总线周期完成，响应于停止时钟信号启动轮询。运行编码以指示停止时钟功能的特殊周期来通知微处理器的单元内部和I / O时钟将停止切换。响应于放置在管线中的NOP微指令，内部和I / O时钟发出信号停止，表示管道没有待处理的指令。执行多个NOP，该数量由I / O时钟停止所需的时间量决定。

2. 发明授权

US06594734B1 Method and apparatus for self modifying code detection using a translation lookaside buffer 有权
标题翻译：使用翻译后备缓冲器自我修改代码检测的方法和装置
公开(公告)号：US06594734B1
公开(公告)日：2003-07-15
申请号：US09466687
申请日：1999-12-20
申请人： Alan Kyker , Chan Lee , Vihang D. Pandya , Roshan Fernando
发明人： Alan Kyker , Chan Lee , Vihang D. Pandya , Roshan Fernando
IPC分类号： G06F1208
CPC分类号： G06F9/3812 , G06F12/0831 , G06F12/0875 , G06F12/1027
摘要： Self modifying code is detected using a translation lookaside buffer in order to provide cache coherency. The translation lookaside buffer has physical page addresses stored therein over which snoops can be performed using the physical memory address of a store into memory. The translation lookaside buffer includes a content addressable memory which not only provides page translation but provides content addressability based on the physical page addresses stored therein. If a match occurs during a snoop using the translation lookaside buffer, it is possible that an SMC occurred within the page of locations stored in memory associated with the matched physical page addresses. To provide finer granularity than a page of addresses, FINE HIT bits are included with each entry in the cache associating information in the cache to portions of a page within memory. Snoop logic performs the comparison of the FINE HIT bits with the respective lower order bits of the physical address to determine if a self modifying code condition has occurred within the portion of memory that may be stored in the cache.
摘要翻译：使用翻译后备缓冲区检测自修改代码，以提供高速缓存一致性。翻译后备缓冲器具有存储在其中的物理页面地址，通过该物理页面地址可以使用存储器的物理存储器地址来执行窥探。翻译后备缓冲器包括内容可寻址存储器，其不仅提供页面翻译，而且基于存储在其中的物理页面地址提供内容可寻址性。如果在使用翻译后备缓冲器的窥探期间发生匹配，则可能在存储在与匹配的物理页地址相关联的存储器中的位置的页面内发生SMC。为了提供比一页地址更精细的粒度，FINE HIT位包括在高速缓存中的每个条目中，将高速缓存中的信息与内存中的页面的部分相关联。侦听逻辑执行FINE HIT位与物理地址的相应较低位的比较，以确定在可能存储在高速缓存中的存储器部分内是否发生了自修改代码条件。

3. 发明授权

US5712826A Apparatus and a method for embedding dynamic state machines in a static environment 失效
标题翻译：用于在动态环境中嵌入动态状态机的装置和方法
公开(公告)号：US5712826A
公开(公告)日：1998-01-27
申请号：US624704
申请日：1996-03-26
申请人： Keng L. Wong , Roshan Fernando
发明人： Keng L. Wong , Roshan Fernando
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： An apparatus and a method for embedding a dynamic state machine in a static integrated circuit environment. A static integrated circuit environment which is capable of suspending operation during a power down clock-stopped condition and resuming operation from a stored state at the conclusion of the power down condition is combined with a dynamic state machine featuring dynamic latches embedded in the static integrated circuit environment. The disclosed dynamic state machine is also configured to suspend operation during the power down condition and resume operation after the power down condition from the stored stated. In addition, both the static integrated circuit environment and the embedded dynamic state machine draw minimal power during the power down condition. With the dynamic state machine embedded in the static integrated circuit environment of the present invention, faster overall circuit operation is realized with less clock capacitance, with less integrated circuit area utilized as well as reduced power consumption.
摘要翻译：一种在静态集成电路环境中嵌入动态状态机的装置和方法。能够在断电时钟停止状态下暂停运行的静态集成电路环境，以及在断电状态结束时从存储状态恢复运行的静态集成电路环境与静态集成电路中嵌入动态锁存器的动态状态机组合环境。所公开的动态状态机还被配置为在停电状态期间暂停操作，并且在从所存储的状态之后的停电状态之后恢复操作。此外，静态集成电路环境和嵌入式动态状态机在断电条件下都能获得最小功率。将动态状态机嵌入到本发明的静态集成电路环境中，通过较少的时钟电容实现更快的整体电路操作，集成电路面积较少，功耗降低。

4. 发明授权

US5471587A Fractional speed bus coupling 失效
标题翻译：分速总线耦合
公开(公告)号：US5471587A
公开(公告)日：1995-11-28
申请号：US954871
申请日：1992-09-30
申请人： Roshan Fernando
发明人： Roshan Fernando
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405
摘要： Apparatus for enabling internal data processing logic including a number of units clocked at a first frequency to operate with an external bus operating at a second frequency that is a fraction m/n of said first frequency. A first bus is connected via readers to data latched for data transfer from the number internal units of the data processing logic to the data latches. A second bus is connected via drivers to the data latches for data transfer from internal bus units to the data latches. The data latches are connected to the external bus. A control circuit connected to the readers and drivers controls the readers and drivers to guarantee that sampling is done when logic is stable. The control circuit includes priority logic for determining priority between the units for permitting a high priority unit to transfer data on the external bus. Upon the condition that m=1 and n is any positive integer, transfer of data from the external bus to the first bus occurs at the point in time that the internal clock and the external clock are aligned. Upon the condition that m=2 and n is any positive odd integer, transfer of data from the external bus to the second bus occurs at the point in time that the internal clock and the external clock are aligned. The priority logic prevents enabling the drivers during any period during which the internal clock and the external clock are not aligned.
摘要翻译：用于使得能够内部数据处理逻辑的装置包括以第一频率计时的多个单元与以所述第一频率的分数m / n的第二频率工作的外部总线进行操作。第一个总线通过读卡器连接到锁存的数据，从数据处理逻辑的数字内部单元传输到数据锁存器。第二总线通过驱动器连接到数据锁存器，用于从内部总线单元传输到数据锁存器。数据锁存器连接到外部总线。连接到读卡器和驱动器的控制电路控制读卡器和驱动器，以保证在逻辑稳定时进行采样。控制电路包括用于确定用于允许高优先级单元在外部总线上传送数据的单元之间的优先级的优先级逻辑。在m = 1且n为任意正整数的情况下，在内部时钟和外部时钟对齐的时间点内，将数据从外部总线传送到第一个总线。在m = 2且n是任何正的奇整数的条件下，在内部时钟和外部时钟对齐的时间点上，将数据从外部总线传送到第二总线。优先级逻辑防止在内部时钟和外部时钟未对齐的任何时间段内启用驱动程序。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式