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1. 发明授权

US5880917A Well resistor for ESD protection of CMOS circuits 失效
公开(公告)号：US5880917A
公开(公告)日：1999-03-09
申请号：US906174
申请日：1997-08-04
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H02H9/00
CPC分类号： H01L27/0288 , H01L27/0266
摘要： A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

2. 发明授权

US06586290B1 Structure for ESD protection in semiconductor chips 失效
标题翻译：半导体芯片ESD保护结构
公开(公告)号：US06586290B1
公开(公告)日：2003-07-01
申请号：US09097481
申请日：1998-06-15
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L218234
CPC分类号： H01L27/0288
摘要： An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.
摘要翻译：用于I / O焊盘的ESD保护结构由在晶体管的有源区域下面的阱电阻器形成。阱电阻器与有源区域串联耦合，并提供额外的电阻，这有助于保护晶体管免受ESD事件的影响。在有源区域上的金属导体具有通过绝缘层形成的有源区域的多个触点以接触有源区域。与晶体管的有源区相邻的附加有源区也耦合到阱电阻器以及向I / O焊盘提供导体的导电层。有源区域被硅化以降低其电阻并增加晶体管的开关速度。 n阱电阻器串联耦合以提供相对于有源区域的大电阻以减少ESD事件的影响。

3. 发明授权

US06507074B2 Structure for ESD protection in semiconductor chips 有权
标题翻译：半导体芯片ESD保护结构
公开(公告)号：US06507074B2
公开(公告)日：2003-01-14
申请号：US09945513
申请日：2001-08-30
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L2362
CPC分类号： H01L27/0288
摘要： An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.
摘要翻译：用于I / O焊盘的ESD保护结构由在晶体管的有源区域下面的阱电阻器形成。阱电阻器与有源区域串联耦合并提供额外的电阻，这有助于保护晶体管免受ESD事件的影响。在有源区域上的金属导体具有通过绝缘层形成的有源区域的多个触点以接触有源区域。与晶体管的有源区相邻的附加有源区也耦合到阱电阻器以及向I / O焊盘提供导体的导电层。有源区域被硅化以降低其电阻并增加晶体管的开关速度。 n阱电阻器串联耦合以提供相对于有源区域的大电阻以减少ESD事件的影响。

4. 发明授权

US6137664A Well resistor for ESD protection of CMOS circuits 有权
标题翻译：用于CMOS电路ESD保护的良好电阻
公开(公告)号：US6137664A
公开(公告)日：2000-10-24
申请号：US231137
申请日：1999-01-15
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H02H9/00
CPC分类号： H01L27/0288 , H01L27/0266
摘要： A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.
摘要翻译：公开了一种用于提供静电放电（ESD）保护的电路。该电路包括一对具有减小的电阻源和漏极的CMOS场效应上拉和下拉晶体管，其中分别在供电和接地总线之间形成在其外部的阱电阻器。在ESD事件期间，阱电阻用于限制通过晶体管的电流，并且减小它们之间的电压降。

5. 发明授权

US5801421A Staggered contact placement on CMOS chip 失效
标题翻译： CMOS芯片交错接触放置
公开(公告)号：US5801421A
公开(公告)日：1998-09-01
申请号：US850278
申请日：1997-05-05
申请人： Joseph C. Sher , Manny K. F. Ma , Stephen L. Casper
发明人： Joseph C. Sher , Manny K. F. Ma , Stephen L. Casper
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/108 , H01L29/41
CPC分类号： H01L23/5226 , H01L2924/0002
摘要： A method and apparatus for increasing the number of contacts provided between two conductive layers separated by an insulator in a semiconductor integrated circuit chip is disclosed. In a first row of contacts, each contact in the row is separated by a distance, L. A second row of contacts is formed parallel to the first row. Each contact in the second row is spaced a distance of L from other contacts in the row. However, the second row is staggered from the first row, such that each contact is halfway between adjacent contacts in the first row. Each contact in the second row is located a distance of L from the two closest contacts in the first row. Successive rows are formed in a similar staggered manner.
摘要翻译：公开了一种用于增加在半导体集成电路芯片中由绝缘体隔开的两个导电层之间提供的触点数量的方法和装置。在第一排触点中，行中的每个触点被隔开一段距离L。第二行触点形成为平行于第一行。第二排中的每个触点与行中的其他触点间隔一定距离L。然而，第二行与第一行交错，使得每个触点位于第一行中的相邻触点之间的中间。第二排中的每个触点位于与第一行中两个最接近的触点的距离L。连续的行以类似的交错方式形成。

6. 发明授权

US5767552A Structure for ESD protection in semiconductor chips 失效
公开(公告)号：US5767552A
公开(公告)日：1998-06-16
申请号：US869513
申请日：1997-06-05
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0288
摘要： An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

7. 发明授权

US5654860A Well resistor for ESD protection of CMOS circuits 失效
标题翻译：用于CMOS电路ESD保护的良好电阻
公开(公告)号：US5654860A
公开(公告)日：1997-08-05
申请号：US515921
申请日：1995-08-16
申请人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
发明人： Stephen L. Casper , Manny K. F. Ma , Joseph C. Sher
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H02H3/20
CPC分类号： H01L27/0288 , H01L27/0266
摘要： A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.
摘要翻译：公开了一种用于提供静电放电（ESD）保护的电路。该电路包括一对具有减小的电阻源和漏极的CMOS场效应上拉和下拉晶体管，其中分别在供电和接地总线之间形成在其外部的阱电阻器。在ESD事件期间，阱电阻用于限制通过晶体管的电流，并且减小它们之间的电压降。

8. 发明授权

US6069492A Voltage compensating CMOS input buffer circuit 失效
标题翻译：电压补偿CMOS输入缓冲电路
公开(公告)号：US6069492A
公开(公告)日：2000-05-30
申请号：US925376
申请日：1997-09-08
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K17/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.
摘要翻译：电压补偿CMOS输入缓冲器将输入TTL信号转换为CMOS逻辑电平，并通过使用n沟道晶体管来补偿变化的电源电压，从而将p沟道对的有效尺寸比改变成组成输入反相器的n沟道晶体管。补偿晶体管可以以增加的电源电压工作，以帮助n沟道输入反相器晶体管偏移通过增加电源电压而其跳变点将被增加的p沟道输入反相器晶体管。随着电源电压的降低，补偿晶体管关闭，使输入逆变器返回原来的大小比例。补偿晶体管的栅极通过两个二极管耦合到电源电压，以控制流过补偿晶体管的电流量。与补偿晶体管串联的另外的跳变点晶体管的栅极耦合到输入信号以帮助稳定跳变点。输出级反相器从输入反相器的输出提供CMOS逻辑电平。

9. 发明授权

US5578941A Voltage compensating CMOS input buffer circuit 失效
公开(公告)号：US5578941A
公开(公告)日：1996-11-26
申请号：US518546
申请日：1995-08-23
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.

10. 发明授权

US6157204A Buffer with adjustable slew rate and a method of providing an adjustable slew rate 有权
公开(公告)号：US6157204A
公开(公告)日：2000-12-05
申请号：US129655
申请日：1998-08-05
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K17/16 , H03K5/12
CPC分类号： H03K17/163
摘要： A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

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