专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140152481A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF DYNAMICALLY MODIFYING AT LEAST ONE CHARACTERISTIC WITHIN A DIGITAL TO ANALOGUE CONVERTER MODULE 有权
标题翻译：集成电路设备和数字模拟转换器模块中的至少一个特性动态修改的方法
公开(公告)号：US20140152481A1
公开(公告)日：2014-06-05
申请号：US14233762
申请日：2011-07-20
申请人： Stephane Dugalleix , Birama Goumballa , Gilles Montoriol
发明人： Stephane Dugalleix , Birama Goumballa , Gilles Montoriol
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/0626 , H03M1/0863 , H03M1/745
摘要： An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
摘要翻译：集成电路装置包括至少一个数模转换器模块。 DAC模块包括具有第一通道端子，第二通道端子和布置成接收参考电压信号的参考电压端子的至少一个电流复制器部件; 所述至少一个当前复制器组件被布置成至少部分地基于接收到的参考电压信号来调节在第一和第二通道端子之间流动的电流。 DAC模块还包括耦合到参考电压端子的至少一个滤波器组件以执行参考电压信号的滤波。

2. 发明授权

US09094032B2 Integrated circuit device and method of dynamically modifying at least one characteristic within a digital to analogue converter module 有权
标题翻译：集成电路装置和动态地修改数模转换器模块内的至少一个特性的方法
公开(公告)号：US09094032B2
公开(公告)日：2015-07-28
申请号：US14233762
申请日：2011-07-20
申请人： Stephane Dugalleix , Birama Goumballa , Gilles Montoriol
发明人： Stephane Dugalleix , Birama Goumballa , Gilles Montoriol
IPC分类号： H03M1/66 , H03M1/06 , H03M1/08 , H03M1/74
CPC分类号： H03M1/06 , H03M1/0626 , H03M1/0863 , H03M1/745
摘要： An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
摘要翻译：集成电路装置包括至少一个数模转换器模块。 DAC模块包括具有第一通道端子，第二通道端子和布置成接收参考电压信号的参考电压端子的至少一个电流复制器部件; 所述至少一个当前复制器组件被布置成至少部分地基于接收到的参考电压信号来调节在第一和第二通道端子之间流动的电流。 DAC模块还包括耦合到参考电压端子的至少一个滤波器组件以执行参考电压信号的滤波。

3. 发明授权

US09628093B2 Charge pump circuit, phase locked loop apparatus, integrated circuit, and method of manufacture of a charge pump 有权
公开(公告)号：US09628093B2
公开(公告)日：2017-04-18
申请号：US14899499
申请日：2013-07-18
申请人： Birama Goumballa , Gilles Montoriol , Didier Salle
发明人： Birama Goumballa , Gilles Montoriol , Didier Salle
IPC分类号： H03L7/06 , H03L7/089 , H03K17/567 , H03L7/18
CPC分类号： H03L7/0896 , H03K17/567 , H03L7/18
摘要： A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

4. 发明授权

US09401723B2 XOR phase detector, phase-locked loop, and method of operating a PLL 有权
标题翻译： XOR相位检测器，锁相环和操作PLL的方法
公开(公告)号：US09401723B2
公开(公告)日：2016-07-26
申请号：US14709686
申请日：2015-05-12
申请人： Gilles Montoriol , Olivier Vincent Doare , Birama Goumballa , Didier Salle
发明人： Gilles Montoriol , Olivier Vincent Doare , Birama Goumballa , Didier Salle
IPC分类号： H03L7/06 , H03L7/097 , H03L7/093 , H03L7/095
CPC分类号： H03L7/1976 , H03L7/085
摘要： An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.
摘要翻译：用于锁相环PLL的XOR相位检测器包括具有用于周期性参考信号的输入的XOR门和连接到PLL的分频器的另一输入。电平移位器具有连接到异或门的输出的电平移位器输入和可连接到PLL的压控振荡器VCO的电平移位器输出。电平转换器可连接低电压供电器和高电平供电器之间，具有高电平和低电平。电平移位器被设置为根据XOR相位检测器的输出端的电压是低还是高来在其输出端输出高电平或低电平。电平移位器还具有用于将高电平设置为设定值电平的设定值输入。

5. 发明授权

US09835715B2 Integrated circuit, radar device and method of calibrating a receiver 有权
公开(公告)号：US09835715B2
公开(公告)日：2017-12-05
申请号：US14660471
申请日：2015-03-17
申请人： Dominique Delbecq , Olivier Doare , Gilles Montoriol
发明人： Dominique Delbecq , Olivier Doare , Gilles Montoriol
IPC分类号： G01S7/40 , G01S13/34 , G01S13/93
CPC分类号： G01S7/4056 , G01S13/34 , G01S13/931 , G01S2007/4073
摘要： An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

6. 发明申请

US20060084403A1 Radio frequency power amplifier 有权
标题翻译：射频功率放大器
公开(公告)号：US20060084403A1
公开(公告)日：2006-04-20
申请号：US10970098
申请日：2004-10-20
申请人： Benjamin Gilsdorf , Gilles Montoriol , David Newman , Jacques Trichet
发明人： Benjamin Gilsdorf , Gilles Montoriol , David Newman , Jacques Trichet
IPC分类号： H04B1/06
CPC分类号： H03F1/30 , H03F1/0211 , H03F3/24 , H03F3/72 , H03F2200/78 , H04B2001/0408
摘要： A radio frequency (RF) power amplification circuit including a power amplifier is provided for preventing breakdown of the power amplifier. The power amplifier includes an input for receiving RF signals and an output for providing amplified RF signals. The RF power amplification circuit also includes a bias circuit coupled to the input of the power amplifier to permit normal operation of the power amplifier when the base current is below a predetermined current threshold and to prevent normal operation of the power amplifier when the base current is above the predetermined current threshold.
摘要翻译：提供了包括功率放大器的射频（RF）功率放大电路，用于防止功率放大器的击穿。功率放大器包括用于接收RF信号的输入和用于提供放大的RF信号的输出。 RF功率放大电路还包括耦合到功率放大器的输入端的偏置电路，以便当基极电流低于预定电流阈值时允许功率放大器的正常操作，并且当基极电流为基极电流时，防止功率放大器的正常工作高于预定电流阈值。

7. 发明申请

US20110285575A1 INTEGRATED CIRCUIT COMPRISING FREQUENCY GENERATION CIRCUITRY FOR CONTROLLING A FREQUENCY SOURCE 有权
标题翻译：包含用于控制频率源的频率发生电路的集成电路
公开(公告)号：US20110285575A1
公开(公告)日：2011-11-24
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S13/02
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

8. 发明申请

US20080211585A1 Adaptive Protection Circuit For a Power Amplifier 有权
标题翻译：功率放大器的自适应保护电路
公开(公告)号：US20080211585A1
公开(公告)日：2008-09-04
申请号：US11911930
申请日：2005-04-18
申请人： Walid Karoui , Gilles Montoriol , Philippe Riondet
发明人： Walid Karoui , Gilles Montoriol , Philippe Riondet
IPC分类号： H03F1/52 , H03F3/04
CPC分类号： H03F1/52 , H03F1/30 , H03F3/19 , H03F2200/451 , H03F2200/462 , H03F2200/477 , H03F2200/78
摘要： A radio frequency device comprises a radio frequency (RF) power amplifier (PA) operably coupled to a protection circuit for minimising voltage standing wave ratio effects, wherein the protection circuit comprises a current limiter indexed to a power supplied to the RF PA.In this manner, the protection circuit combines detection of both current and voltage increase in order to provide a direct feedback on the final RF PA stage via a bias control.
摘要翻译：射频设备包括可操作地耦合到保护电路以用于最小化电压驻波比效应的射频（RF）功率放大器（PA），其中保护电路包括被分配到提供给RF PA的功率的限流器。以这种方式，保护电路组合了电流和电压增加的检测，以便通过偏置控制在最终RF PA级上提供直接反馈。

9. 发明授权

US07113054B2 Arrangement and method impedance matching 有权
标题翻译：布置和方法阻抗匹配
公开(公告)号：US07113054B2
公开(公告)日：2006-09-26
申请号：US10468178
申请日：2002-07-28
申请人： Phillipe Riondet , Gilles Montoriol , Jaques Trichet
发明人： Phillipe Riondet , Gilles Montoriol , Jaques Trichet
IPC分类号： H03H7/38
CPC分类号： H01L24/49 , H01L23/66 , H01L24/48 , H01L2223/6611 , H01L2223/6644 , H01L2224/48227 , H01L2224/4911 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01031 , H01L2924/01043 , H01L2924/01058 , H01L2924/01074 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03H7/383 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node (204a) for receiving an output current to be impedance matched; a second node (212, 214) for receiving output current from the first node; a first current conductor (202c) for carrying current from the first node to the second node; a third node (204b) for receiving output current from the second node; and a second current conductor (202d) for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance. The current conductors may be wire bonds, the arrangement may include a capacitor integrated in a power amplifier IC module, in which the capacitor may be provided in a separate IC from the power amplifier, the arrangement may utilise a plurality of impedance matching cells, and the wire bonds may be interdigitated across the semiconductor die. This provides the following advantages: easy to implement; increased accuracy of matching; requires few external components; easy to manufacture; no need for dedicated design flow; requires only standard IC production and test tools; uses low loss matching networks; involves only a small increase in die size (due to integration of capacitor), but the total size of the solution may be significantly reduced (e.g., by 50%) because of the reduced number of external components.
摘要翻译：一种用于阻抗匹配（例如功率放大器）的装置和方法，包括用于接收待阻抗匹配的输出电流的第一节点（204a）; 用于从第一节点接收输出电流的第二节点（212,214）; 用于承载从第一节点到第二节点的电流的第一电流导体（202c）; 用于从第二节点接收输出电流的第三节点（204b）; 以及用于将电流从所述第二节点传送到所述第三节点的第二电流导体（202d），由此所述第一和第二电流导体被紧密地定位，使得它们的电感是它们的自感和它们相互的负和之和电感。电流导体可以是引线接合，该布置可以包括集成在功率放大器IC模块中的电容器，其中电容器可以设置在与功率放大器分离的IC中，该装置可以利用多个阻抗匹配单元，以及引线键可跨越半导体管芯交错。这提供了以下优点：易于实现; 提高匹配精度; 需要很少的外部组件; 易于制造; 无需专用设计流程; 只需要标准的IC生产和测试工具; 使用低损耗匹配网络; 仅涉及芯片尺寸的小的增加（由于电容器的集成），但是由于外部部件的数量减少，所以溶液的总尺寸可以显着降低（例如，50％）。

10. 发明授权

US08654006B2 Integrated circuit comprising frequency generation circuitry for controlling a frequency source 有权
标题翻译：集成电路，包括用于控制频率源的频率产生电路
公开(公告)号：US08654006B2
公开(公告)日：2014-02-18
申请号：US13145122
申请日：2009-02-13
申请人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
发明人： Christophe Landez , Hugues Beaulaton , Thierry Cassagnes , Stephane Colomines , Robert G. Gach , Akbar Ghazinour , Hao Li , Gilles Montoriol , Didier Salle , Pierre Savary
IPC分类号： G01S7/28
CPC分类号： G01S7/35 , G01S7/032 , G01S13/34 , G01S13/931 , G01S2013/9325 , H03C3/0925 , H03L7/1976
摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.
摘要翻译：集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式