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1. 发明授权

US06456961B1 Method and apparatus for creating testable circuit designs having embedded cores 有权
标题翻译：用于创建具有嵌入式核心的可测试电路设计的方法和装置
公开(公告)号：US06456961B1
公开(公告)日：2002-09-24
申请号：US09302699
申请日：1999-04-30
申请人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
发明人： Srinivas Patil , Wu-Tung Cheng , Paul J. Reuter
IPC分类号： G06F1750
CPC分类号： G01R31/318505
摘要： A computer-implemented method and apparatus for creating a testable circuit design that includes one or more embedded cores. The method includes identifying an embedded core within the circuit design; associating certain pins of the embedded core with pins of the circuit design; and inserting into the circuit design access circuitry coupling the certain connection pins of the embedded core to the associated pins of the circuit design. The method further includes providing test vectors for the embedded core; and generating test vectors for the circuit design by mapping the core test vectors applicable to the certain pins of the embedded core to the associated pins of the circuit design. The cores within the circuit design can then be tested after manufacture by applying the design test vectors to the circuit design.
摘要翻译：一种用于创建包括一个或多个嵌入式核心的可测试电路设计的计算机实现的方法和装置。该方法包括识别电路设计内的嵌入式核心; 将嵌入式核心的某些引脚与电路设计的引脚相关联; 并将插入到嵌入式芯的某些连接引脚的电路设计访问电路插入电路设计的相关引脚。该方法还包括提供用于嵌入式核心的测试向量; 以及通过将适用于嵌入式核心的某些引脚的核心测试向量映射到电路设计的相关引脚来生成用于电路设计的测试向量。然后可以通过将设计测试矢量应用于电路设计，然后在制造后对电路设计中的核心进行测试。

2. 发明授权

US06934897B2 Scheduling the concurrent testing of multiple cores embedded in an integrated circuit 有权
标题翻译：调度嵌入在集成电路中的多个内核的并发测试
公开(公告)号：US06934897B2
公开(公告)日：2005-08-23
申请号：US10210794
申请日：2002-07-31
申请人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
发明人： Nilanjan Mukherjee , Chien-Chung Tsai , Wu-Tung Cheng , Omer Ghazi Samman , Yahya M. Z. Mustafa , Paul J. Reuter , Yu Huang , Sudhakar Mannapuram Reddy
IPC分类号： G01R31/3193 , G01R31/28
CPC分类号： G01R31/3193
摘要： Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.
摘要翻译：描述了用于调度嵌入在集成电路中的多个核的并发测试的方法。通过将问题解决为二进制包装问题并使用修改后的二维或三维二进制包装启发式来进行测试调度。多个核心的测试表示为至少用于测试核心和核心测试时间的集成电路引脚的功能。表示可以包括测试核心所需的峰值功率的第三维度。测试计划表示为具有至少集成电路引脚和集成电路测试时间的尺寸的存储区。箱可以包括峰值功率的第三维度。多核的调度是通过将多个核心测试表示拟合到bin来实现的。

3. 发明授权

US07424660B2 Synchronization point across different memory BIST controllers 有权
标题翻译：跨不同内存BIST控制器的同步点
公开(公告)号：US07424660B2
公开(公告)日：2008-09-09
申请号：US11397822
申请日：2006-04-03
申请人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
发明人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/12015 , G11C29/14 , G11C29/56012 , G11C2029/0401 , G11C2029/2602
摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.
摘要翻译：公开了一种用于使用嵌入在集成电路（IC）中的多个内置自测（BIST）控制器测试存储器的电路。通过允许同步状态，BIST控制器在存储器测试期间被带到同步点。来自IC上的输出引脚的输出信号表示存在与自动测试设备（ATE）的同步状态。 ATE接收到输出信号后，通过IC输入引脚发出一个恢复信号，导致控制器进入同步状态。 ATE通过延迟恢复信号来控制同步状态长度。同步状态可用于参数化测试算法，例如保留和IDDQ测试。可以通过软件设计工具将同步状态并入用户定义的算法，该工具可生成可操作以将同步状态应用于算法的BIST控制器的HDL描述。

4. 发明授权

US07036064B1 Synchronization point across different memory BIST controllers 有权
公开(公告)号：US07036064B1
公开(公告)日：2006-04-25
申请号：US09872212
申请日：2001-05-31
申请人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
发明人： Omar Kebichi , Wu-Tung Cheng , Christopher John Hill , Paul J. Reuter , Yahya M. Z. Mustafa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/12015 , G11C29/14 , G11C29/56012 , G11C2029/0401 , G11C2029/2602
摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

5. 发明授权

US08280688B2 Compactor independent direct diagnosis of test hardware 有权
标题翻译：压缩机独立直接诊断测试硬件
公开(公告)号：US08280688B2
公开(公告)日：2012-10-02
申请号：US12790049
申请日：2010-05-28
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G06F11/30 , G06F11/00
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

6. 发明授权

US08209572B2 Testing embedded memories in an integrated circuit 有权
标题翻译：在集成电路中测试嵌入式存储器
公开(公告)号：US08209572B2
公开(公告)日：2012-06-26
申请号：US12941404
申请日：2010-11-08
申请人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号： G06F17/50 , G11C29/00 , G01R31/28
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

7. 发明授权

US07840865B2 Built-in self-test of integrated circuits using selectable weighting of test patterns 有权
标题翻译：使用可选择的测试模式加权来集成电路的内置自检
公开(公告)号：US07840865B2
公开(公告)日：2010-11-23
申请号：US11973084
申请日：2007-10-05
申请人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
发明人： Liyang Lai , Wu-Tung Cheng , Thomas Hans Rinderknecht
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.
摘要翻译：公开了一种内置自检（BIST）电路，可以实现高故障覆盖。另外，公开了一种用于实现BIST电路的方法。在一个方面，BIST电路包括多个扫描链，其接收用于测试集成电路的测试图案。伪随机模式生成器向扫描链提供测试模式。重量选择逻辑位于扫描链和伪随机模式发生器之间，并控制加载到扫描链中的测试图案的权重。在另一方面，权重选择逻辑可以在每个扫描单元的基础上切换测试图案的加权。因此，随着扫描链的加载，权重选择逻辑可以有效地在被加载到扫描链中的测试模式之间切换。

8. 发明授权

US07836366B2 Defect localization based on defective cell diagnosis 有权
标题翻译：基于缺陷细胞诊断的缺陷定位
公开(公告)号：US07836366B2
公开(公告)日：2010-11-16
申请号：US11876430
申请日：2007-10-22
申请人： Manish Sharma , Wu-Tung Cheng
发明人： Manish Sharma , Wu-Tung Cheng
IPC分类号： G01R31/28 , G01R31/14 , G01R31/02 , G01R31/26 , G06F11/00
CPC分类号： G01R31/318569 , G01R31/2846
摘要： Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.
摘要翻译：所描述的各种实施例中的一种检测集成电路的单元中的缺陷的方法，其分析在测试的捕获阶段期间施加到单元的输入的运行条件，其中产生故障指示的失败的测试图案，并且分析运行在测试捕获阶段期间应用的条件，其中可观察到的通过模式不提供故障指示。从分析可以确定真实故障激励条件和通过激励条件，并用于识别缺陷是在集成电路的单元还是互连线上。

9. 发明申请

US20090172486A1 TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT 有权
标题翻译：在一体化电路中测试嵌入式存储器
公开(公告)号：US20090172486A1
公开(公告)日：2009-07-02
申请号：US12400664
申请日：2009-03-09
申请人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号： G01R31/3187 , G06F11/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

10. 发明授权

US07434131B2 Flexible memory built-in-self-test (MBIST) method and apparatus 有权
标题翻译：灵活内存内置自检（MBIST）方法和装置
公开(公告)号：US07434131B2
公开(公告)日：2008-10-07
申请号：US11282938
申请日：2005-11-18
申请人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
发明人： Nilanjan Mukherjee , Xiaogang Du , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.
摘要翻译：公开了可编程存储器内置的自检（MBIST）方法，装置和系统。所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。

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