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1. 发明授权

US08356222B2 Fault diagnosis for non-volatile memories 有权
标题翻译：非易失性存储器的故障诊断
公开(公告)号：US08356222B2
公开(公告)日：2013-01-15
申请号：US12718822
申请日：2010-03-05
申请人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

2. 发明申请

US20120272110A1 Test Generator For Low Power Built-In Self-Test 有权
标题翻译：用于低功耗内置自检的测试发生器
公开(公告)号：US20120272110A1
公开(公告)日：2012-10-25
申请号：US13451527
申请日：2012-04-19
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318385 , G01R31/3187
摘要： Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
摘要翻译：本发明的方面涉及基于BIST的低功率测试。低功率测试发生器可以包括伪随机模式发生器单元，触发控制单元，被配置为基于由伪随机模式发生器单元生成的比特序列数据产生切换控制数据;以及保持寄存器单元，被配置为产生低功率测试图案数据通过基于从触发控制单元接收到的切换控制数据，在各种时间段期间以常数值替换来自伪随机模式发生器单元的一些或全部输出的数据。低功率测试发生器还可以包括移相器，其被配置为组合用于驱动扫描链的低功率测试图案数据的位。

3. 发明授权

US08290738B2 Low power scan testing techniques and apparatus 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US08290738B2
公开(公告)日：2012-10-16
申请号：US13049844
申请日：2011-03-16
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（EDT）架构）集成）。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

4. 发明授权

US08051352B2 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US08051352B2
公开(公告)日：2011-11-01
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

5. 发明授权

US07900104B2 Test pattern compression for an integrated circuit test environment 有权
标题翻译：用于集成电路测试环境的测试模式压缩
公开(公告)号：US07900104B2
公开(公告)日：2011-03-01
申请号：US12405409
申请日：2009-03-17
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案。

6. 发明授权

US07877656B2 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07877656B2
公开(公告)日：2011-01-25
申请号：US12352994
申请日：2009-01-13
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并适于接收解压缩的测试图案。

7. 发明申请

US20100146350A1 TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS 有权
标题翻译：用于减少功率耗散和供电电流的测试生成方法
公开(公告)号：US20100146350A1
公开(公告)日：2010-06-10
申请号：US12703057
申请日：2010-02-09
申请人： Xijiang Lin , Janusz Rajski
发明人： Xijiang Lin , Janusz Rajski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31721 , G01R31/318357 , G01R31/318575
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.
摘要翻译：这里公开的是用于生成测试图案的方法，装置和系统的代表性实施例，可用作测试图案生成过程的一部分（例如，用于自动测试图案生成器（ATPG）软件工具））。在一个示例性实施例中，为电路设计的状态元素（例如，扫描单元）确定保持概率。产生针对电路设计中的一个或多个故障的测试立方体。在一个特定实现中，测试多维数据集最初包括指定的一个或多个故障的值，并且还包括未指定的值。通过至少部分由保存概率确定的值来指定至少一部分未指定值来修改测试立方体，并存储。

8. 发明申请

US20100138708A1 DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS 有权
标题翻译：用于测试模式的低功率分解的分解器
公开(公告)号：US20100138708A1
公开(公告)日：2010-06-03
申请号：US12641150
申请日：2009-12-17
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

9. 发明授权

US07729884B2 Compactor independent direct diagnosis of test hardware 有权
标题翻译：压缩机独立直接诊断测试硬件
公开(公告)号：US07729884B2
公开(公告)日：2010-06-01
申请号：US11267221
申请日：2005-11-04
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G06F11/30 , G06F11/00
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received including entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，包括指示针对链图案的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

10. 发明授权

US07653851B2 Phase shifter with reduced linear dependency 有权
标题翻译：移相器具有减少的线性依赖性
公开(公告)号：US07653851B2
公开(公告)日：2010-01-26
申请号：US12412267
申请日：2009-03-26
申请人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
发明人： Janusz Rajski , Jerzy Tyszer , Nagesh Tamarapalli
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31813 , G01R31/318385 , G01R31/318547 , G01R31/318594
摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
摘要翻译：公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

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