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1. 发明授权

US07839319B2 High speed parallel procesing digita path for SAR ADC 有权
标题翻译： SAR ADC的高速并行处理数字通路
公开(公告)号：US07839319B2
公开(公告)日：2010-11-23
申请号：US12254678
申请日：2008-10-20
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

2. 发明申请

US20090102694A1 High Speed Parallel Procesing Digita Path for SAR ADC 有权
标题翻译： SAR ADC的高速并行处理数字通路
公开(公告)号：US20090102694A1
公开(公告)日：2009-04-23
申请号：US12254678
申请日：2008-10-20
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

3. 发明授权

US07439898B1 Parallel digital processing for reducing delay in SAR ADC logic 有权
标题翻译：用于减少SAR ADC逻辑延迟的并行数字处理
公开(公告)号：US07439898B1
公开(公告)日：2008-10-21
申请号：US11755761
申请日：2007-05-31
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

4. 发明授权

US08624764B2 Test circuits and methods for redundant electronic systems 有权
标题翻译：冗余电子系统的测试电路和方法
公开(公告)号：US08624764B2
公开(公告)日：2014-01-07
申请号：US13371297
申请日：2012-02-10
申请人： Jeremy Gorbold
发明人： Jeremy Gorbold
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , G01R31/3167 , G05B9/03 , H03M1/0678 , H03M1/12
摘要： A redundant analog-to-digital conversion system can include at least one input multiplexer, first and second redundant analog-to-digital converters, a comparison circuit and an output multiplexer. The at least one input multiplexer can receive a plurality of analog input signals and output at lest one multiplexed analog input signal. The first and second redundant analog-to-digital converters can convert the at least one multiplexed analog input signal to respectively generate first and second digital output signals, the first digital output having a greater digital resolution than the second digital output. The comparison circuit can produce a comparison output signal as a function of a comparison of a plurality of most significant corresponding bit pairs of the first and second digital output signals. The output multiplexer can produce a multiplexed output including information from the comparison output signal and one of the digital output signals.
摘要翻译：冗余模数转换系统可以包括至少一个输入多路复用器，第一和第二冗余模数转换器，比较电路和输出多路复用器。所述至少一个输入多路复用器可以接收多个模拟输入信号，并输出至少一个复用的模拟输入信号。第一和第二冗余模数转换器可以将至少一个复用的模拟输入信号转换成分别产生第一和第二数字输出信号，第一数字输出具有比第二数字输出更大的数字分辨率。比较电路可以产生比较输出信号作为第一和第二数字输出信号的多个最高有效对应位对的比较的函数。输出多路复用器可以产生包括来自比较输出信号和数字输出信号之一的信息的复用输出。

5. 发明授权

US09158727B2 Addressable integrated circuit and method thereof 有权
标题翻译：可寻址集成电路及其方法
公开(公告)号：US09158727B2
公开(公告)日：2015-10-13
申请号：US12771302
申请日：2010-04-30
申请人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
发明人： Jeremy Gorbold , James Gibbons , Tadhg Creedon , Katherine O'Riordan , John Reidy , John Morrissey
IPC分类号： G01R19/175 , G01R19/14 , G06F3/00 , G06F3/01 , G06F13/42 , G06F12/06 , G01R31/36
CPC分类号： G06F13/4247 , G01R31/3658 , G06F12/0661
摘要： An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.
摘要翻译：在菊花链网络中寻址集成电路的示例性方法和系统。在示例性方法中，可以将集成电路的地址初始化为预定的初始地址。集成电路可以接收包括类型标识符和地址字段的命令。基于类型标识符，可以确定命令的类型。作为决定的结果，从地址字段读取地址。读取地址可以存储在寄存器中。该地址可以被修改，并且可以被输出。在接收到数据或命令时，可以通过错误检查算法来确认包括接收到的命令中的数据的数据的完整性。

6. 发明授权

US09958507B2 Channel verification of multiple channels on one chip 有权
公开(公告)号：US09958507B2
公开(公告)日：2018-05-01
申请号：US13467735
申请日：2012-05-09
申请人： Jeremy Gorbold , Colin McIntosh , Niall McDermott , Katherine O'Riordan , Robert Parle , James Stegen
发明人： Jeremy Gorbold , Colin McIntosh , Niall McDermott , Katherine O'Riordan , Robert Parle , James Stegen
IPC分类号： G01N27/416 , G01R31/36
CPC分类号： G01R31/3658
摘要： A battery monitoring system and method are disclosed. A battery monitor compares data in parallel register files. If voltage deviation above a certain threshold is detected in one register file, the system generates an alert that a fault exists upstream in the system. In order to better detect errors, the system may intentionally alter the voltages on the batteries to be monitored.

7. 发明申请

US20120286792A1 Channel Verification of Multiple Channels on One Chip 有权
标题翻译：单芯片多通道通道验证
公开(公告)号：US20120286792A1
公开(公告)日：2012-11-15
申请号：US13467735
申请日：2012-05-09
申请人： Jeremy Gorbold , Colin McIntosh , Niall McDermott , Katherine O'Riordan , Robert Parle , James Stegen
发明人： Jeremy Gorbold , Colin McIntosh , Niall McDermott , Katherine O'Riordan , Robert Parle , James Stegen
IPC分类号： G01R31/36
CPC分类号： G01R31/3658
摘要： A battery monitoring system and method are disclosed. A battery monitor compares data in parallel register files. If voltage deviation above a certain threshold is detected in one register file, the system generates an alert that a fault exists upstream in the system. In order to better detect errors, the system may intentionally alter the voltages on the batteries to be monitored.
摘要翻译：公开了一种电池监视系统和方法。电池监视器将并行寄存器文件中的数据进行比较。如果在一个寄存器文件中检测到高于某个阈值的电压偏差，则系统会生成系统上游存在故障的警报。为了更好地检测错误，系统可能有意改变要监控的电池的电压。

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