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1. 发明申请

US20070190728A1 LOW RESISTANCE GATE FOR POWER MOSFET APPLICATIONS AND METHOD OF MANUFACTURE 有权
标题翻译：功率MOSFET应用的低电阻栅和制造方法
公开(公告)号：US20070190728A1
公开(公告)日：2007-08-16
申请号：US11467997
申请日：2006-08-29
申请人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
发明人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/66734 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/4958 , H01L29/4966 , H01L29/513
摘要： A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
摘要翻译：如下形成沟槽栅场效应晶体管。在半导体区域中形成沟槽，随后是在沟槽的侧壁和底部衬垫并延伸到与沟槽相邻的台面区域上的电介质层。导电种子层形成在电介质层上的沟槽的底部。在导电种子层上生长低电阻材料，其中低电阻材料对导电种子层是选择性的。

2. 发明授权

US07807536B2 Low resistance gate for power MOSFET applications and method of manufacture 有权
标题翻译：功率MOSFET应用的低电阻门和制造方法
公开(公告)号：US07807536B2
公开(公告)日：2010-10-05
申请号：US11467997
申请日：2006-08-29
申请人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , Kent Naylor
发明人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , Kent Naylor
IPC分类号： H01L21/336
CPC分类号： H01L29/66734 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/4958 , H01L29/4966 , H01L29/513
摘要： A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.
摘要翻译：如下形成沟槽栅场效应晶体管。在半导体区域中形成沟槽，随后是在沟槽的侧壁和底部衬垫并延伸到与沟槽相邻的台面区域上的电介质层。导电种子层形成在电介质层上的沟槽的底部。在导电种子层上生长低电阻材料，其中低电阻材料对导电种子层是选择性的。

3. 发明授权

US08592277B2 Method of forming low resistance gate for power MOSFET applications 有权
标题翻译：形成用于功率MOSFET应用的低电阻栅极的方法
公开(公告)号：US08592277B2
公开(公告)日：2013-11-26
申请号：US12891147
申请日：2010-09-27
申请人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
发明人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
IPC分类号： H01L21/336
CPC分类号： H01L29/66734 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/4958 , H01L29/4966 , H01L29/513
摘要： A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.
摘要翻译：形成沟槽栅场效应晶体管的方法包括在半导体区域中形成沟槽，然后形成衬在沟槽的侧壁和底表面的电介质层。该方法还包括：在沟槽的底表面上形成第一多晶硅层。该方法还包括：在第一多晶硅层的暴露表面上形成导电材料层，并在导电材料层的暴露表面上形成第二多晶硅层。该方法还包括进行快速热处理以使第一多晶硅层，第二多晶硅层和导电材料层发生反应。

4. 发明申请

US20110014763A1 Method of Forming Low Resistance Gate for Power MOSFET Applications 有权
标题翻译：形成功率MOSFET应用的低电阻门的方法
公开(公告)号：US20110014763A1
公开(公告)日：2011-01-20
申请号：US12891147
申请日：2010-09-27
申请人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
发明人： Sreevatsa Sreekantham , Ihsiu Ho , Fred Session , James Kent Naylor
IPC分类号： H01L21/336
CPC分类号： H01L29/66734 , H01L29/42368 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/4958 , H01L29/4966 , H01L29/513
摘要： A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.
摘要翻译：沟槽栅场效应晶体管包括以下步骤。在半导体区域中形成沟槽，然后在沟槽的侧壁和底部衬有介电层。在沟槽中形成凹陷的多晶硅层。在凹陷的多晶硅层上形成高导电性覆盖层，并与其接触。进行快速热处理以使凹陷的多晶硅层和高导电性盖层发生反应。

5. 发明申请

US20100308402A1 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的3D通道架构
公开(公告)号：US20100308402A1
公开(公告)日：2010-12-09
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

6. 发明申请

US20090194812A1 Structure for Making a Top-side Contact to a Substrate 有权
标题翻译：用于与基材进行顶部接触的结构
公开(公告)号：US20090194812A1
公开(公告)日：2009-08-06
申请号：US12359670
申请日：2009-01-26
申请人： Chun-Tai Wu , Ihsiu Ho
发明人： Chun-Tai Wu , Ihsiu Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/66712 , H01L21/743 , H01L29/0653 , H01L29/0696 , H01L29/7397 , H01L29/7809 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material.
摘要翻译：半导体结构包括具有凹陷部分的起始半导体衬底。半导体材料形成在凹部中并具有比起始半导体衬底更高的电阻率。体区域在半导体材料中延伸，并且具有与半导体材料相反的导电类型。源区域在体区域中延伸，并且具有与身体区域相反的导电类型。栅极电极相邻地延伸但与身体区域绝缘。第一互连层延伸并且与起始半导体衬底的非凹陷部分接触。第一互连层和非凹陷部分提供与半导体材料下面的起始半导体衬底的部分的顶侧电接触。

7. 发明授权

US08003522B2 Method for forming trenches with wide upper portion and narrow lower portion 有权
标题翻译：用于形成具有宽的上部和窄的下部的沟槽的方法
公开(公告)号：US08003522B2
公开(公告)日：2011-08-23
申请号：US12327425
申请日：2008-12-03
申请人： Hui Chen , Ihsiu Ho , Stacy W. Hall , Briant Harward , Hossein Paravi
发明人： Hui Chen , Ihsiu Ho , Stacy W. Hall , Briant Harward , Hossein Paravi
IPC分类号： H01L21/00
CPC分类号： H01L29/7813 , H01L21/3085 , H01L21/3086 , H01L29/41766 , H01L29/4236 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.
摘要翻译：一种形成半导体结构的方法包括以下步骤。在半导体区域上形成硬掩模层。硬掩模层具有比其外部部分薄的内部部分，并且内部部分限定半导体区域的暴露的表面积。通过半导体区域的暴露的表面区域去除半导体区域的一部分。去除硬掩模层的较薄部分以暴露较薄部分下面的半导体区域的表面区域。通过半导体区域的所有暴露的表面区域去除半导体区域的附加部分，从而形成具有比下部更宽的上部的沟槽。

8. 发明申请

US20100123225A1 Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same 失效
标题翻译：用于晶圆级芯片尺寸的半导体晶片结构，功率器件，封装及其使用系统及其制作方法
公开(公告)号：US20100123225A1
公开(公告)日：2010-05-20
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

9. 发明授权

US08536042B2 Method of forming a topside contact to a backside terminal of a semiconductor device 有权
标题翻译：在半导体器件的背面端子上形成顶部接触的方法
公开(公告)号：US08536042B2
公开(公告)日：2013-09-17
申请号：US12982509
申请日：2010-12-30
申请人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
发明人： John T. Andrews , Hamza Yilmaz , Bruce Marchant , Ihsiu Ho
IPC分类号： H01L21/44
CPC分类号： H01L29/7811 , H01L24/12 , H01L29/0657 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7809 , H01L29/7813 , H01L29/872 , H01L2924/01055 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/3025 , H01L2924/00
摘要： A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
摘要翻译：形成垂直导电半导体器件的工艺包括提供具有顶侧表面和背面的半导体衬底。半导体衬底用作垂直传导器件的端子，用于在操作期间偏压垂直传导器件。该工艺还包括形成在半导体衬底的顶侧表面上延伸但在到达半导体衬底的边缘之前终止的外延层，以沿着半导体衬底的周边形成凹陷区域。该方法还包括形成延伸到凹陷区域中但在到达半导体衬底的边缘之前终止的互连层。互连层在凹陷区域中电接触半导体衬底的顶侧表面，从而提供与半导体衬底的顶侧接触。

10. 发明申请

US20130087852A1 EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES 审中-公开
标题翻译：功率半导体器件的边缘终止结构
公开(公告)号：US20130087852A1
公开(公告)日：2013-04-11
申请号：US13267712
申请日：2011-10-06
申请人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
发明人： Suku Kim , Joseph Andrew Yedinak , Ihsiu Ho
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： Edge termination structures for power semiconductor devices and methods for making such structures are described. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures. Other embodiments are described.
摘要翻译：描述用于功率半导体器件的边缘终端结构及其制造方法。功率半导体器件（或功率器件）包含其上具有外延层的衬底，形成在外延层中的基本上平行的有源沟槽的阵列，其中有源沟槽包含具有绝缘栅极导电层的晶体管结构，超级结或与有源沟槽相邻的屏蔽区域; 围绕有源沟槽的外围沟槽，以及在外延层的上表面内的源极接触区域，其中栅极导电层在超结或屏蔽区域上延伸并在周围的周边沟槽上方延伸。这种配置允许边缘终端结构在包含PN超结构结构的功率MOSFET器件中与宽范围的击穿电压一起使用。描述其他实施例。

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