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1. 发明申请

US20100308402A1 3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的3D通道架构
公开(公告)号：US20100308402A1
公开(公告)日：2010-12-09
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

2. 发明授权

US08072027B2 3D channel architecture for semiconductor devices 有权
标题翻译：半导体器件的3D通道架构
公开(公告)号：US08072027B2
公开(公告)日：2011-12-06
申请号：US12480065
申请日：2009-06-08
申请人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
发明人： Suku Kim , Dan Calafut , Ihsiu Ho , Dan Kinzer , Steven Sapp , Ashok Challa , Seokjin Jo , Mark Larsen
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/407 , H01L29/4236 , H01L29/4933
摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
摘要翻译：描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近源区。因此，在主线状沟槽内形成较小的支柱沟槽。这种架构产生基本垂直于常规线形通道排列的附加通道区域。常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。描述其他实施例。

3. 发明授权

US07393749B2 Charge balance field effect transistor 有权
标题翻译：电荷平衡场效应晶体管
公开(公告)号：US07393749B2
公开(公告)日：2008-07-01
申请号：US11450903
申请日：2006-06-08
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/336 , H01L23/62
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.
摘要翻译：场效应晶体管如下形成。提供了具有在半导体区域上延伸的具有第二导电性的外延层的第一导电类型的半导体区域。形成延伸穿过外延层并终止在半导体区域中的沟槽。执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。形成沟槽每一侧的第一导电类型的源区。

4. 发明申请

US20050167742A1 Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20050167742A1
公开(公告)日：2005-08-04
申请号：US11026276
申请日：2004-12-29
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
摘要翻译：公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

5. 发明申请

US20110303975A1 Field effect transistor with self-aligned source and heavy body regions 有权
标题翻译：具有自对准源和重体区域的场效应晶体管
公开(公告)号：US20110303975A1
公开(公告)日：2011-12-15
申请号：US13152041
申请日：2011-06-02
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
摘要翻译：场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。多个沟槽包括多个门控沟槽和多个非门控沟槽。第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。电介质材料填充每个门控沟槽和非门控沟槽的底部。栅极电极设置在每个门控沟槽中。第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

6. 发明申请

US20060281249A1 Charge balance field effect transistor 有权
标题翻译：电荷平衡场效应晶体管
公开(公告)号：US20060281249A1
公开(公告)日：2006-12-14
申请号：US11450903
申请日：2006-06-08
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.
摘要翻译：场效应晶体管如下形成。提供了具有延伸在半导体区域上的具有第二导电性的外延层的第一导电类型的半导体区域。形成延伸穿过外延层并终止在半导体区域中的沟槽。执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。形成沟槽每一侧的第一导电类型的源区。

7. 发明授权

US08193570B2 Synchronous buck converter using shielded gate field effect transistors 有权
标题翻译：同步降压转换器采用屏蔽栅场效应晶体管
公开(公告)号：US08193570B2
公开(公告)日：2012-06-05
申请号：US12845999
申请日：2010-07-29
申请人： Steven Sapp , Ashok Challa , Christopher B. Kocon
发明人： Steven Sapp , Ashok Challa , Christopher B. Kocon
IPC分类号： H01L27/108
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/7803
摘要： A synchronous buck converter includes a high-side switch and a low-side switch serially coupled to one another. The low-side switch includes a field effect transistor that comprises: a trench extending into a drift region of the field effect transistor; a shield electrode in a lower portion of the trench, wherein the shield electrode is insulated from the drift region by a shield dielectric; a gate electrode in the trench over the shield electrode, wherein the gate electrode is insulated from the shield electrode by an inter-electrode dielectric; source regions adjacent the trench; a source metal contacting the source regions; and a resistive element having one end contacting the shield electrode and another end contacting the source metal in the field effect transistor.
摘要翻译：同步降压转换器包括彼此串联耦合的高侧开关和低侧开关。低侧开关包括场效应晶体管，其包括：延伸到场效应晶体管的漂移区域的沟槽; 在所述沟槽的下部中的屏蔽电极，其中所述屏蔽电极通过屏蔽电介质与所述漂移区域绝缘; 在所述屏蔽电极上的沟槽中的栅电极，其中所述栅电极通过电极间电介质与所述屏蔽电极绝缘; 与沟槽相邻的源区; 源极金属与源极区域接触; 以及电阻元件，其一端接触屏蔽电极，另一端接触场效应晶体管中的源极金属。

8. 发明授权

US07768064B2 Structure and method for improving shielded gate field effect transistors 有权
标题翻译：屏蔽栅场效应晶体管的结构和方法
公开(公告)号：US07768064B2
公开(公告)日：2010-08-03
申请号：US11620002
申请日：2007-01-04
申请人： Steven Sapp , Ashok Challa , Christopher B. Kocon
发明人： Steven Sapp , Ashok Challa , Christopher B. Kocon
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/7803
摘要： A field effect transistor is disclosed. In one embodiment, the field effect transistor includes a trench extending into a drift region of the field effect transistor. A shield electrode in a lower portion of the trench is insulated from the drift region by a shield dielectric. A gate electrode in the trench over the shield electrode is insulated from the shield electrode by an inter-electrode dielectric. A source region is formed adjacent the trench. A resistive element is coupled to the shield electrode and to a source region in the field effective transistor.
摘要翻译：公开了一种场效应晶体管。在一个实施例中，场效应晶体管包括延伸到场效应晶体管的漂移区的沟槽。沟槽下部的屏蔽电极通过屏蔽电介质与漂移区绝缘。屏蔽电极上的沟槽中的栅电极通过电极间绝缘体与屏蔽电极绝缘。在沟槽附近形成源区。电阻元件耦合到屏蔽电极和场有效晶体管中的源极区域。

9. 发明授权

US07514322B2 Shielded gate field effect transistor 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US07514322B2
公开(公告)日：2009-04-07
申请号：US12125242
申请日：2008-05-22
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/336 , H01L23/62
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.
摘要翻译： FET包括半导体区域中的沟槽。沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

10. 发明申请

US20080258213A1 Shielded Gate Field Effect Transistor 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US20080258213A1
公开(公告)日：2008-10-23
申请号：US12125242
申请日：2008-05-22
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.
摘要翻译： FET包括半导体区域中的沟槽。沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

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