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1. 发明申请

US20190004112A1 In-Field System Testing 审中-公开
公开(公告)号：US20190004112A1
公开(公告)日：2019-01-03
申请号：US15636762
申请日：2017-06-29
申请人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
发明人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
IPC分类号： G01R31/317 , H04L12/26 , G01R31/26
摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

2. 发明授权

US08473890B2 Timing error sampling generator and a method of timing testing 失效
标题翻译：定时误差采样发生器和定时测试方法
公开(公告)号：US08473890B2
公开(公告)日：2013-06-25
申请号：US13460605
申请日：2012-04-30
申请人： Alexander Tetelbaum , Sreejit Chakravarty
发明人： Alexander Tetelbaum , Sreejit Chakravarty
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A timing error sampling generator, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.
摘要翻译：提供了一种定时误差采样发生器，一种执行定时测试的方法和一个单元库。在一个实施例中，定时误差采样发生器包括：（1）具有输入和输出的保持延迟元件，并且被配置为通过向在所述输入处接收到的时钟信号提供第一预定延迟来在所述输出处提供保持违反延迟信号，所述第一预定延迟对应于要被监视的路径的保持违规时间;以及（2）具有耦合到所述保持延迟元件的所述输入的第一输入的保持逻辑元件，耦合到所述保持延迟的所述输出的第二输入元件和所述保持逻辑元件被配置为响应于所述第一和第二输入以在所述第一和第二输入处的逻辑电平处于相同电平时提供时钟保持信号的输出。

3. 发明授权

US08418008B2 Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit 有权
标题翻译：在集成电路上应用包括扫描时钟修改器的可变扫描时钟的测试技术
公开(公告)号：US08418008B2
公开(公告)日：2013-04-09
申请号：US12337629
申请日：2008-12-18
申请人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
发明人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318552
摘要： A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.
摘要翻译：扫描时钟修改器，提供可变扫描时钟的方法，包括扫描时钟修改器的IC和包括扫描时钟修改器的单元的库。在一个实施例中，扫描时钟修改器包括：（1）逻辑电路，被配置为基于测试扫描时钟信号和第一时钟控制信号提供至少一个选择的时钟信号，测试扫描时钟信号和第一时钟控制从所述测试设备接收的信号和（2）配置成基于所述至少一个所选择的时钟信号和从所述测试设备接收的至少一个其它时钟控制信号提供扫描时钟信号的比较逻辑，其中所述第一和所述至少一个其他时钟控制信号是不同的时钟控制信号。

4. 发明授权

US06502004B1 Method and apparatus for extracting bridges from an integrated circuit layout 失效
标题翻译：从集成电路布局中提取电桥的方法和装置
公开(公告)号：US06502004B1
公开(公告)日：2002-12-31
申请号：US09442119
申请日：1999-11-17
申请人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
发明人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
IPC分类号： G06F1750
CPC分类号： G01R31/3183 , G01R31/31705 , G01R31/31707
摘要： A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size.
摘要翻译：桥式故障提取器。用于从集成电路布局执行故障提取的计算机实现的方法包括从要分析的一组缺陷尺寸的最大缺陷尺寸确定来自布局的最大临界区域，其中每个最大临界区域对应于网络名称对。最大关键区域然后通过网络名称对本地合并，以确定每个网络对的最大关键区域的联合面积。缺陷尺寸小于最大缺陷尺寸的关键区域从最大关键区域确定，通过网络名称对本地合并，以确定每个较小缺陷大小的每个网络名称对的关键区域的联合区域。

5. 发明授权

US08793549B2 Low-cost design for register file testability 有权
标题翻译：低成本设计注册文件可测试性
公开(公告)号：US08793549B2
公开(公告)日：2014-07-29
申请号：US12854682
申请日：2010-08-11
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G06F11/00 , G11C29/16
CPC分类号： G11C29/16 , G11C2207/007
摘要： A self-test module for use in an electronic device includes a test controller and a memory. The memory is configured to receive test vectors from the test controller. A comparator is configured to receive the test data from the memory via an output data path. A strobing buffer is located in the output data path between an output from the memory and an input to the comparator. The strobing buffer is configured to selectively enable the test vectors to propagate from the memory output to the comparator input.
摘要翻译：用于电子设备的自检模块包括测试控制器和存储器。存储器被配置为从测试控制器接收测试向量。比较器被配置为经由输出数据路径从存储器接收测试数据。选通缓冲器位于存储器的输出和比较器的输入之间的输出数据路径中。选通缓冲器被配置为选择性地使测试向量从存储器输出传播到比较器输入。

6. 发明授权

US08711645B2 Victim port-based design for test area overhead reduction in multiport latch-based memories 有权
标题翻译：受害者基于端口的设计，用于降低多端口基于锁存器的存储器中的测试区域开销
公开(公告)号：US08711645B2
公开(公告)日：2014-04-29
申请号：US13431614
申请日：2012-03-27
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G11C29/50 , G11C11/401 , G11C29/02 , G11C29/34
CPC分类号： G11C29/50 , G11C7/1075 , G11C8/16 , G11C11/401 , G11C29/02 , G11C29/32 , G11C29/34
摘要： A multiport latch-based memory device includes a latch array, a plurality of first multiplexers, and a second multiplexer. The latch array is responsive to output data from an input data register in a functional mode associated with the latch-based memory device. The plurality of first multiplexers is responsive to output data from the latch array in the functional mode. The plurality of first multiplexers is responsive to output data from the input data register in a test mode associated with the latch-based memory device. The second multiplexer selectively provides output data from the plurality of first multiplexers to the input data register in the test mode, thereby providing a data path bypassing the latch array in the test mode. Embodiments of a corresponding method and computer-readable medium are also provided.
摘要翻译：多端口基于锁存器的存储器件包括锁存器阵列，多个第一复用器和第二多路复用器。锁存器阵列以与基于锁存器的存储器件相关联的功能模式响应来自输入数据寄存器的输出数据。多个第一多路复用器在功能模式下响应来自锁存器阵列的输出数据。多个第一多路复用器响应于与基于锁存器的存储器件相关联的测试模式中的来自输入数据寄存器的输出数据。第二复用器在测试模式中选择性地将多个第一多路复用器的输出数据提供给输入数据寄存器，从而在测试模式下提供绕过锁存器阵列的数据路径。还提供了相应方法和计算机可读介质的实施例。

7. 发明授权

US08090965B1 System and method for testing memory power management modes in an integrated circuit 失效
标题翻译：在集成电路中测试存储器电源管理模式的系统和方法
公开(公告)号：US08090965B1
公开(公告)日：2012-01-03
申请号：US12104996
申请日：2008-04-17
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F11/00
CPC分类号： G06F11/267
摘要： A memory controller, a method of testing memory power management modes in an integrated circuit and an integrated circuit. In one embodiment, the memory controller includes a power management mode test controller couplable to a test access port and at least one memory core and configured to respond to a signal provided via the test access port by providing an ordered signal-setting sequence to the at least one memory core to cause the at least one memory core to enter into and exit from at least one memory power management mode.
摘要翻译：存储器控制器，测试集成电路中的存储器电源管理模式的方法和集成电路。在一个实施例中，存储器控制器包括可耦合到测试访问端口和至少一个存储器核心的电源管理模式测试控制器，并且被配置为响应于经由测试访问端口提供的信号，通过向at提供有序的信号设置序列至少一个存储器核心，以使所述至少一个存储器核心进入和退出至少一个存储器电源管理模式。

8. 发明申请

US20100153895A1 TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND SETUP VIOLATIONS OF AN INTEGRATED CIRCUIT AND A METHOD OF TIMING TESTING 失效
标题翻译：时序错误采样发生器，用于集成电路保持和设置违规的关键路径监视器和时序测试方法
公开(公告)号：US20100153895A1
公开(公告)日：2010-06-17
申请号：US12334403
申请日：2008-12-12
申请人： Alexander Tetelbaum , Sreejit Chakravarty
发明人： Alexander Tetelbaum , Sreejit Chakravarty
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.
摘要翻译：定时误差采样发生器，路径监视器，IC，执行定时测试的方法和单元库。在一个实施例中，定时误差采样发生器包括：（1）具有输入和输出的保持延迟元件，并且被配置为通过向在所述输入处接收到的时钟信号提供第一预定延迟来在所述输出处提供保持违反延迟信号，所述第一预定延迟对应于要被监视的路径的保持违规时间;以及（2）具有耦合到所述保持延迟元件的所述输入的第一输入的保持逻辑元件，耦合到所述保持延迟的所述输出的第二输入元件和所述保持逻辑元件被配置为响应于所述第一和第二输入以在所述第一和第二输入处的逻辑电平处于相同电平时提供时钟保持信号的输出。

9. 发明授权

US08499230B2 Critical path monitor for an integrated circuit and method of operation thereof 失效
标题翻译：集成电路的关键路径监视器及其操作方法
公开(公告)号：US08499230B2
公开(公告)日：2013-07-30
申请号：US12247992
申请日：2008-10-08
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G06F11/00
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.
摘要翻译：路径监视器，监视路径的方法，集成电路和标准逻辑元件库。在一个实施例中，路径监视器包括：（1）延迟元件，其具有可耦合到与被监控路径相关联的时钟触发器的输入的输入，并且被配置为提供预定延迟，以及（2）时钟异或门，其具有时钟输入，耦合到延迟元件的输出的第一输入，可连接到时钟触发器的输出的第二输入和时钟异或门被配置为响应于时钟信号的输出仅在第一输入和第二输入的逻辑电平不同时提供错误信号。

10. 发明授权

US08464198B1 Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit 失效
标题翻译：电子设计自动化工具和方法，用于使用非敏感关键路径信息来减少集成电路中的漏电功率
公开(公告)号：US08464198B1
公开(公告)日：2013-06-11
申请号：US12182330
申请日：2008-07-30
申请人： Sreejit Chakravarty
发明人： Sreejit Chakravarty
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An electronic design automation (EDA) tool and a method of employing unsensitized critical path information to reduce leakage power in a circuit. In one embodiment, the EDA tool includes: (1) an unsensitizable path identifier configured to receive information regarding designed devices in a circuit and information regarding identified critical paths therein, analyze a logical behavior of the circuit and identify critical and noncritical gates in unsensitizable ones of the critical paths thereof and (2) a transistor designator coupled to the unsensitizable path identifier and configured to designate relatively low threshold voltage transistors for use in the critical gates and designate relatively high threshold voltage transistors for use in the noncritical gates.
摘要翻译：电子设计自动化（EDA）工具和采用未加密关键路径信息以减少电路中泄漏功率的方法。在一个实施例中，EDA工具包括：（1）不可识别的路径标识符，被配置为接收关于电路中设计的设备的信息以及关于其中所识别的关键路径的信息，分析电路的逻辑行为并识别不可识别的关键和非关键门的关键路径和（2）耦合到不可感知路径标识符并被配置为指定用于临界门中的相对低阈值电压晶体管的晶体管指示符，并且指定用于非临界门中的相对高的阈值电压晶体管。

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