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1. 发明授权

US09331855B2 Apparatus, system, and method for providing attribute identity control associated with a processor 有权
标题翻译：用于提供与处理器相关联的属性标识控制的设备，系统和方法
公开(公告)号：US09331855B2
公开(公告)日：2016-05-03
申请号：US13174940
申请日：2011-07-01
申请人： David A. Brown , Adil Karrar , Michael Neve de Mevergnies , Sergiu D. Ghetie , Shahrokh Shahidzadeh
发明人： David A. Brown , Adil Karrar , Michael Neve de Mevergnies , Sergiu D. Ghetie , Shahrokh Shahidzadeh
IPC分类号： G08C17/02 , H04L9/00 , H04L9/32 , G06F21/73
CPC分类号： H04L9/3234 , G06F21/73 , H04L2209/805
摘要： Described herein are an apparatus, system, and method for attribute identity control in a processor. The apparatus comprises a logic unit including a radio-frequency identification (RFID) tag comprising a non-volatile memory; and a processor operable to access the non-volatile memory, wherein the non-volatile memory for storing an attribute identity associated with a group of processors, the attribute identity being different from an identity of the processor.
摘要翻译：这里描述了用于处理器中的属性标识控制的装置，系统和方法。该装置包括一个逻辑单元，该逻辑单元包括一个包括非易失性存储器的射频识别（RFID）标签; 以及可操作以访问所述非易失性存储器的处理器，其中所述非易失性存储器用于存储与一组处理器相关联的属性标识，所述属性标识不同于所述处理器的标识。

2. 发明授权

US08590040B2 Runtime platform firmware verification 有权
标题翻译：运行时平台固件验证
公开(公告)号：US08590040B2
公开(公告)日：2013-11-19
申请号：US12976523
申请日：2010-12-22
申请人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
发明人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
IPC分类号： G06F21/00
CPC分类号： G06F21/572
摘要： Embodiments of the invention are directed towards logic and/or modules stored in processor secure storage to determine whether a first platform firmware image (e.g., basic input/output system (BIOS), device read-only memory (ROM), manageability engine firmware) loaded onto a processor cache is valid. The processor executes the first platform firmware image if it is determined to be valid. If the first platform image is determined to be invalid, a second platform firmware image is located. If this platform firmware image is determined to be valid, the processor will execute said second platform image.In some embodiments of the invention, the determination of whether the first platform firmware image is valid is based, at least in part, on verification of a digital signature associated with the first platform firmware image. The digital signature may be created, for example, from a private key, wherein the digital signature is verified via a public key.
摘要翻译：本发明的实施例针对存储在处理器安全存储器中的逻辑和/或模块来确定第一平台固件映像（例如，基本输入/输出系统（BIOS），设备只读存储器（ROM），可管理性引擎固件）加载到处理器缓存中是有效的。如果判定为有效，则处理器执行第一平台固件映像。如果第一平台图像被确定为无效，则定位第二平台固件图像。如果该平台固件图像被确定为有效，则处理器将执行所述第二平台图像。在本发明的一些实施例中，确定第一平台固件图像是否有效是至少部分地基于与第一平台固件图像相关联的数字签名的验证。可以例如从私钥来创建数字签名，其中通过公钥验证数字签名。

3. 发明申请

US20160179646A1 DELAYED AUTHENTICATION DEBUG POLICY 有权
标题翻译：延迟认证调查政策
公开(公告)号：US20160179646A1
公开(公告)日：2016-06-23
申请号：US14580588
申请日：2014-12-23
申请人： Michael Neve De Mevergnies , Hermann W. Gartler , Michael S. Bair
发明人： Michael Neve De Mevergnies , Hermann W. Gartler , Michael S. Bair
IPC分类号： G06F11/25 , G06F11/27
CPC分类号： G01R31/31719 , G01R31/31705 , G01R31/3177 , G06F11/00 , G06F11/25 , G06F11/27
摘要： A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.
摘要翻译：诸如处理器或片上系统（SoC）的底盘平台包括实现包括策略生成器的调试机箱安全系统的逻辑，以控制来自测试访问端口的访问。策略生成器可以将调试策略分发到在本地强制调试策略的至少一个逻辑块。调试策略可以包括延迟的认证策略，其中分发调试资产，并且机箱平台最初被锁定以防止经由测试访问端口的调试访问。经验证的调试用户可以稍后解锁机箱平台，以启用调试操作。调试策略还可以包括实时执行策略和即时调试策略。

4. 发明申请

US20150033338A1 HARDENING DATA TRANSMISSIONS AGAINST POWER SIDE CHANNEL ANALYSIS 有权
标题翻译：加强数据传输，防止电源通道分析
公开(公告)号：US20150033338A1
公开(公告)日：2015-01-29
申请号：US13952301
申请日：2013-07-26
申请人： Michael Neve De Mevergnies , Manoj Sastry , Ioannis Schoinas
发明人： Michael Neve De Mevergnies , Manoj Sastry , Ioannis Schoinas
IPC分类号： H04L29/06
CPC分类号： H04L63/1475 , H04L9/003 , H04L2209/34
摘要： Embodiments of an invention for hardening data transmissions against power side channel attacks are disclosed. In one embodiment, a system includes a first agent and a second agent. The first agent is to transmit an encoded datum through an interface in a plurality of encoded packets. The second agent is to receive each of the plurality of encoded packets from the interface and decode each of the encoded packets to generate a plurality of decoded packets. Each of the encoded packets has the same Hamming weight. The Hamming distance between any two consecutively transmitted encoded packets is constant.
摘要翻译：公开了用于强化针对电源侧信道攻击的数据传输的发明的实施例。在一个实施例中，系统包括第一代理和第二代理。第一代理是通过多个编码分组中的接口发送编码数据。第二代理是接收来自接口的多个编码包中的每一个，并解码每个编码包以产生多个解码包。每个编码包具有相同的汉明权重。任何两个连续发送的编码包之间的汉明距离是恒定的。

5. 发明申请

US20120167205A1 RUNTIME PLATFORM FIRMWARE VERIFICATION 有权
标题翻译：运行平台固件验证
公开(公告)号：US20120167205A1
公开(公告)日：2012-06-28
申请号：US12976523
申请日：2010-12-22
申请人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
发明人： Sergiu D. Ghetie , Shahrokh Shahidzadeh , Michael Neve de Mevergnies , Adil Karrar , Vincent J. Zimmer
IPC分类号： G06F21/00
CPC分类号： G06F21/572
摘要： Embodiments of the invention are directed towards logic and/or modules stored in processor secure storage to determine whether a first platform firmware image (e.g., basic input/output system (BIOS), device read-only memory (ROM), manageability engine firmware) loaded onto a processor cache is valid. The processor executes the first platform firmware image if it is determined to be valid. If the first platform image is determined to be invalid, a second platform firmware image is located. If this platform firmware image is determined to be valid, the processor will execute said second platform image.In some embodiments of the invention, the determination of whether the first platform firmware image is valid is based, at least in part, on verification of a digital signature associated with the first platform firmware image. The digital signature may be created, for example, from a private key, wherein the digital signature is verified via a public key.
摘要翻译：本发明的实施例针对存储在处理器安全存储器中的逻辑和/或模块来确定第一平台固件映像（例如，基本输入/输出系统（BIOS），设备只读存储器（ROM），可管理性引擎固件）加载到处理器缓存中是有效的。如果判定为有效，则处理器执行第一平台固件映像。如果第一平台图像被确定为无效，则定位第二平台固件图像。如果该平台固件图像被确定为有效，则处理器将执行所述第二平台图像。在本发明的一些实施例中，确定第一平台固件图像是否有效是至少部分地基于与第一平台固件图像相关联的数字签名的验证。可以例如从私钥来创建数字签名，其中通过公钥验证数字签名。

6. 发明申请

US20100041182A1 METHOD, SYSTEM, AND APPARATUS FOR A SECURE BUS ON A PRINTED CIRCUIT BOARD 有权
标题翻译：用于打印电路板上的安全总线的方法，系统和装置
公开(公告)号：US20100041182A1
公开(公告)日：2010-02-18
申请号：US12604697
申请日：2009-10-23
申请人： Michael Neve de Mevergnies , Jean-Pierre Seifert
发明人： Michael Neve de Mevergnies , Jean-Pierre Seifert
IPC分类号： H01L21/56
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译：一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。

7. 发明授权

US07633168B2 Method, system, and apparatus for a secure bus on a printed circuit board 失效
标题翻译：用于印刷电路板上安全总线的方法，系统和装置
公开(公告)号：US07633168B2
公开(公告)日：2009-12-15
申请号：US11476956
申请日：2006-06-28
申请人： Michael Neve de Mevergnies , Jean-Pierre Seifert
发明人： Michael Neve de Mevergnies , Jean-Pierre Seifert
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H05K1/181 , H01L23/585 , H01L2924/0002 , H05K1/0275 , H05K2201/09781 , H05K2201/10159 , H05K2201/10515 , H05K2201/10689 , Y02P70/611 , H01L2924/00
摘要： A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area.
摘要翻译：一种方法，装置和系统，该装置在一些实施例中包括印刷电路板（PCB），位于PCB上并电连接到PCB的集成电路（IC），位于PCB和IC之间的芯片，以及在PCB和IC之间形成封闭的边界屏障并且与PCB接触以限定在内部容纳区域内完全包含芯片的内部容纳区域。

8. 发明申请

US20190004112A1 In-Field System Testing 审中-公开
公开(公告)号：US20190004112A1
公开(公告)日：2019-01-03
申请号：US15636762
申请日：2017-06-29
申请人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
发明人： Sreejit Chakravarty , Oscar Mendoza , Ramasubramanian Rajamani , Bryan J. Gran , Sorin Iacobovici , Neel Shah , Michael Neve de Mevergnies , John Cruz Mejia , Amy L. Santoni
IPC分类号： G01R31/317 , H04L12/26 , G01R31/26
摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

9. 发明授权

US09235719B2 Apparatus, system, and method for providing memory access control 有权
标题翻译：用于提供存储器访问控制的装置，系统和方法
公开(公告)号：US09235719B2
公开(公告)日：2016-01-12
申请号：US13992222
申请日：2011-09-29
申请人： Michael Neve De Mevergnies , Knut S. Grimsrud , Sergiu D. Ghetie , Prasun Ratn , Shahrokh Shahidzadeh
发明人： Michael Neve De Mevergnies , Knut S. Grimsrud , Sergiu D. Ghetie , Prasun Ratn , Shahrokh Shahidzadeh
IPC分类号： G06F21/00 , G06F21/62 , G06F17/30 , G06F21/60 , G06F21/44 , G06F21/56 , G06F21/57 , G06F21/79 , G06F11/14
CPC分类号： G06F21/62 , G06F11/1415 , G06F17/30289 , G06F21/445 , G06F21/568 , G06F21/572 , G06F21/602 , G06F21/6218 , G06F21/79
摘要： Described herein are apparatus, system, and method for providing memory access control to protect software (e.g., firmware backup) and other data. The method comprises providing, by a processor, a protected storage area in a memory for storing backup image of software; detecting corruption in the software; accessing the backup image of the software from the protected storage area; and updating the corrupted software using the backup image, wherein the protected storage area is a reserved storage area of the memory.
摘要翻译：这里描述了用于提供存储器访问控制以保护软件（例如，固件备份）和其他数据的装置，系统和方法。该方法包括由处理器提供存储器中的保护存储区域，用于存储软件的备份图像; 检测软件中的腐败; 从受保护的存储区域访问软件的备份映像; 以及使用所述备份图像更新所述损坏的软件，其中所述受保护存储区域是所述存储器的保留存储区域。

10. 发明申请

US20150058510A1 VIRTUALIZING INTERRUPT PRIORITY AND DELIVERY 审中-公开
标题翻译：虚拟中断优先和交付
公开(公告)号：US20150058510A1
公开(公告)日：2015-02-26
申请号：US14538941
申请日：2014-11-12
申请人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
发明人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
IPC分类号： G06F13/26 , G06F9/455
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
摘要翻译：公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。在一个实施例中，处理器包括指令硬件和执行硬件。指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式检测多个虚拟机退出事件中的任何一个。执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。

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