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1. 发明授权

US06598211B2 Scaleable approach to extracting bridges from a hierarchically described VLSI layout 失效
公开(公告)号：US06598211B2
公开(公告)日：2003-07-22
申请号：US09823807
申请日：2001-03-30
申请人： Sujit T. Zachariah , Sreejit Chakravarty
发明人： Sujit T. Zachariah , Sreejit Chakravarty
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A bridge fault extractor. For one aspect, one of a plurality of segments of a hierarchically described integrated circuit layout is flattened to produce an annotated list of rectangles. A fault list corresponding to the segment is then computed using the annotated list of rectangles. The fault list is then merged with any prior-generated fault list, and the actions of flattening, computing and merging are repeated for each of the plurality of segments to produce a fault list for the integrated circuit.

2. 发明授权

US06519499B1 Method and apparatus for extracting bridges from an integrated circuit layout 失效
标题翻译：从集成电路布局中提取电桥的方法和装置
公开(公告)号：US06519499B1
公开(公告)日：2003-02-11
申请号：US09475714
申请日：1999-12-30
申请人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
发明人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
IPC分类号： G06F1750
CPC分类号： G01R31/3183 , G01R31/31705 , G01R31/31707
摘要： A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout in a two-net analysis mode includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size. In a multi-net analysis mode, overlap rectangles are determined by net-name pair. The overlap rectangles are then used to calculate critical areas for two-net and multi-net bridges for each defect size in a set of defect sizes to be analyzed. In one aspect, similar to the two-net analysis mode, overlap rectangles are first determined for the maximum defect size and are resized for smaller defect sizes.
摘要翻译：桥式故障提取器。用于在双网分析模式中从集成电路布局执行故障提取的计算机实现的方法包括从所述布局确定用于要分析的一组缺陷尺寸的最大缺陷尺寸的最大临界面积，其中每个最大临界面积对应于网名对。然后，最大关键区域通过网络名称对本地合并，以确定每个网络名称对的最大关键区域的联合区域。缺陷尺寸小于最大缺陷尺寸的关键区域从最大关键区域确定，并通过网络名称对本地合并，以确定每个较小缺陷尺寸的每个网络名称对的关键区域的联合面积。在多网分析模式中，重叠矩形由网络名称对决定。然后，重叠矩形用于计算要分析的一组缺陷尺寸中每个缺陷尺寸的双网和多网桥的关键区域。在一个方面，类似于双网分析模式，首先确定最大缺陷尺寸的重叠矩形，并且针对较小的缺陷尺寸进行调整大小。

3. 发明授权

US06502004B1 Method and apparatus for extracting bridges from an integrated circuit layout 失效
标题翻译：从集成电路布局中提取电桥的方法和装置
公开(公告)号：US06502004B1
公开(公告)日：2002-12-31
申请号：US09442119
申请日：1999-11-17
申请人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
发明人： Sreejit Chakravarty , Sujit T. Zachariah , Carl D. Roth
IPC分类号： G06F1750
CPC分类号： G01R31/3183 , G01R31/31705 , G01R31/31707
摘要： A bridge fault extractor. A computer-implemented method for performing fault extraction from an integrated circuit layout includes determining maximum critical areas from the layout for a maximum defect size of a set of defect sizes to be analyzed wherein each maximum critical area corresponds to a net-name pair. The maximum critical areas are then locally merged by net-name pair to determine an area of a union of maximum critical areas for each net-name pair. Critical areas for defect sizes smaller than the maximum defect size are determined from the maximum critical areas and locally merged by net-name pair to determine an area of a union of critical areas for each net-name pair for each smaller defect size.
摘要翻译：桥式故障提取器。用于从集成电路布局执行故障提取的计算机实现的方法包括从要分析的一组缺陷尺寸的最大缺陷尺寸确定来自布局的最大临界区域，其中每个最大临界区域对应于网络名称对。最大关键区域然后通过网络名称对本地合并，以确定每个网络对的最大关键区域的联合面积。缺陷尺寸小于最大缺陷尺寸的关键区域从最大关键区域确定，通过网络名称对本地合并，以确定每个较小缺陷大小的每个网络名称对的关键区域的联合区域。

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