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1. 发明授权

US07739640B2 Method and apparatus for static timing analysis in the presence of a coupling event and process variation 失效
标题翻译：在存在耦合事件和过程变化的情况下进行静态时序分析的方法和装置
公开(公告)号：US07739640B2
公开(公告)日：2010-06-15
申请号：US11622979
申请日：2007-01-12
申请人： Soroush Abbaspour , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Soroush Abbaspour , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.
摘要翻译：在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口，其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

2. 发明申请

US20080172642A1 METHOD AND APPARATUS FOR STATIC TIMING ANALYSIS IN THE PRESENCE OF A COUPLING EVENT AND PROCESS VARIATION 失效
标题翻译：联系事件和过程变化存在的静态时序分析方法与装置
公开(公告)号：US20080172642A1
公开(公告)日：2008-07-17
申请号：US11622979
申请日：2007-01-12
申请人： Soroush Abbaspour , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Soroush Abbaspour , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.
摘要翻译：在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口，其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。

3. 发明授权

US08359563B2 Moment-based characterization waveform for static timing analysis 有权
标题翻译：用于静态时序分析的基于时刻的表征波形
公开(公告)号：US08359563B2
公开(公告)日：2013-01-22
申请号：US12542042
申请日：2009-08-17
申请人： Soroush Abbaspour , Peter Feldmann , David Ling , Chandramouli Visweswariah
发明人： Soroush Abbaspour , Peter Feldmann , David Ling , Chandramouli Visweswariah
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.
摘要翻译：在一个实施例中，本发明是用于静态时序分析的基于时刻的表征波形。用于将与集成电路的栅极相关联的定时波形映射到表征波形的方法的一个实施例包括使用处理器执行步骤，包括：计算定时波形的一个或多个时刻并根据时刻定义表征波形。

4. 发明申请

US20080250370A1 REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权
标题翻译：在数字电路的统计静态时序分析中代表和传播变量电压波形
公开(公告)号：US20080250370A1
公开(公告)日：2008-10-09
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译：描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

5. 发明授权

US07814448B2 Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits 有权
标题翻译：在数字电路的统计静态时序分析中表征和传播变分电压波形
公开(公告)号：US07814448B2
公开(公告)日：2010-10-12
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译：描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

6. 发明申请

US20090077515A1 Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise 失效
标题翻译：串扰导致噪声的约束进攻器集合选择方法
公开(公告)号：US20090077515A1
公开(公告)日：2009-03-19
申请号：US11855323
申请日：2007-09-14
申请人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
发明人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
摘要翻译：执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响。给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

7. 发明授权

US07685549B2 Method of constrained aggressor set selection for crosstalk induced noise 失效
标题翻译：串扰引起噪声的约束入侵者集合选择方法
公开(公告)号：US07685549B2
公开(公告)日：2010-03-23
申请号：US11855323
申请日：2007-09-14
申请人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
发明人： Debjit Sinha , Soroush Abbaspour , Ayesha Akhter , Gregory M. Schaeffer , David J. Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
摘要翻译：执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响。给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。

8. 发明申请

US20120124542A1 Method and System for Optimizing a Device With Current Source Models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

9. 发明申请

US20120123725A1 PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US20120123725A1
公开(公告)日：2012-05-17
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅里叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

10. 发明授权

US08396910B2 Efficient compression and handling of model library waveforms 失效
标题翻译：模型库波形的有效压缩和处理
公开(公告)号：US08396910B2
公开(公告)日：2013-03-12
申请号：US12265765
申请日：2008-11-06
申请人： Soroush Abbaspour , Peter Feldmann , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Safar Hatami
IPC分类号： G06F7/00
CPC分类号： H03M7/30
摘要： A system and method for waveform compression includes preprocessing a collection of waveforms representing cell and/or interconnect response waveforms and constructing a representative waveform basis using linear algebra to create basis waveforms for a larger set of waveforms. The collection waveforms are represented as linear combination coefficients of an adaptive subset of the basis waveforms to compress an amount of stored information needed to reproduce the collection of waveforms. The representation of coefficients may be further compressed by, e.g., analytic representation.
摘要翻译：用于波形压缩的系统和方法包括预处理表示单元和/或互连响应波形的波形的集合，并使用线性代数构建代表性的波形基础，以创建更大的一组波形的基本波形。收集波形被表示为基本波形的自适应子集的线性组合系数，以压缩再现波形收集所需的存储信息量。可以通过例如分析表示来进一步压缩系数的表示。

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