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1. 发明授权

US08359563B2 Moment-based characterization waveform for static timing analysis 有权
标题翻译：用于静态时序分析的基于时刻的表征波形
公开(公告)号：US08359563B2
公开(公告)日：2013-01-22
申请号：US12542042
申请日：2009-08-17
申请人： Soroush Abbaspour , Peter Feldmann , David Ling , Chandramouli Visweswariah
发明人： Soroush Abbaspour , Peter Feldmann , David Ling , Chandramouli Visweswariah
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.
摘要翻译：在一个实施例中，本发明是用于静态时序分析的基于时刻的表征波形。用于将与集成电路的栅极相关联的定时波形映射到表征波形的方法的一个实施例包括使用处理器执行步骤，包括：计算定时波形的一个或多个时刻并根据时刻定义表征波形。

2. 发明申请

US20120124542A1 Method and System for Optimizing a Device With Current Source Models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

3. 发明申请

US20120123725A1 PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US20120123725A1
公开(公告)日：2012-05-17
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅里叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

4. 发明授权

US08463571B2 Performing reliability analysis of signal wires 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US08463571B2
公开(公告)日：2013-06-11
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅立叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

5. 发明授权

US08020129B2 Multiple voltage threshold timing analysis for a digital integrated circuit 有权
标题翻译：数字集成电路的多电压阈值时序分析
公开(公告)号：US08020129B2
公开(公告)日：2011-09-13
申请号：US12021723
申请日：2008-01-29
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
摘要翻译：描述了用于对数字集成电路执行多个电压阈值时序分析的方法。在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。互连电路模型检索部件被配置为获得互连电路的模型。多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。

6. 发明授权

US07788617B2 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis 失效
标题翻译：在定时分析期间建模和采用CMOS栅极的方法和输出负载相关的引脚电容
公开(公告)号：US07788617B2
公开(公告)日：2010-08-31
申请号：US12043455
申请日：2008-03-06
申请人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
发明人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.
摘要翻译：一种精确的方法来计算电容与电容相关的引脚上的电容。该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。产生来自压摆和输出负载的针电容表的RC / RLC网络。所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。

7. 发明申请

US20090193373A1 MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT 有权
标题翻译：用于数字集成电路的多电压阈值时序分析
公开(公告)号：US20090193373A1
公开(公告)日：2009-07-30
申请号：US12021723
申请日：2008-01-29
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
摘要翻译：描述了用于对数字集成电路执行多个电压阈值时序分析的方法。在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。互连电路模型检索部件被配置为获得互连电路的模型。多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。

8. 发明授权

US08549452B2 Method for supporting multiple libraries characterized at different process, voltage and temperature points 失效
标题翻译：支持以不同过程，电压和温度点为特征的多个库的方法
公开(公告)号：US08549452B2
公开(公告)日：2013-10-01
申请号：US12774766
申请日：2010-05-06
申请人： Revanta Banerji , Soroush Abbaspour , Peter Feldmann , Hemlata Gupta
发明人： Revanta Banerji , Soroush Abbaspour , Peter Feldmann , Hemlata Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/08 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.
摘要翻译：一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。

9. 发明授权

US08515725B2 Characterization of nonlinear cell macro model for timing analysis 失效
标题翻译：定时分析非线性单元宏观模型的表征
公开(公告)号：US08515725B2
公开(公告)日：2013-08-20
申请号：US12958637
申请日：2010-12-02
申请人： Peter Feldmann , Sampath Dechu , Soroush Abbaspour , Ratan Singh
发明人： Peter Feldmann , Sampath Dechu , Soroush Abbaspour , Ratan Singh
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036 , G06F2217/10
摘要： A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior.
摘要翻译：一种用于对半导体器件结构进行建模的系统，方法和计算机程序产品。实现的系统和方法包括通过在电路输入端口上施加至少一个输入波形来执行电路的仿真，并且利用至少一个输出负载来加载输出端口; 在电路仿真的连续时间步骤中确定输入端口上的电压值Vi，输出端口上的电压值Vo，以及相应输入和输出端口上的电流值（ia）和（ib）。然后，根据模拟的每个连续时间步长的相应电流值，分别计算作为Vi和Vo的函数的至少一个充电值（Qa（Vi，Vo））和（Qb（Vi，Vo））电压值; 以及从所述至少一个电荷值产生非线性电荷源，所述非线性电荷源用于对所述电池的动态行为进行建模。因此，通过捕获自然数字电路单元行为来确定压控电荷源（VCCS）。

10. 发明授权

US08239810B2 Method and system for optimizing a device with current source models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US08239810B2
公开(公告)日：2012-08-07
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

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