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1. 发明授权

US06828229B2 Method of manufacturing interconnection line in semiconductor device 有权
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US06828229B2
公开(公告)日：2004-12-07
申请号：US10081661
申请日：2002-02-22
申请人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
发明人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31116 , H01L21/31144
摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.
摘要翻译：提供了一种在半导体器件中形成互连线的方法。在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。在第一蚀刻停止件上形成第一层间绝缘层。在第一层间绝缘层上形成第二蚀刻阻挡层。在第二蚀刻停止件上形成第二层间绝缘层。使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。保护层被去除。位于通孔底部的第一蚀刻停止部分被去除。形成填充通孔和沟槽并与下导电层电连接的上导电层。

2. 发明授权

US07183195B2 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler 有权
标题翻译：使用混合低k电介质和无碳无机填料制造微电子器件的双镶嵌互连的方法
公开(公告)号：US07183195B2
公开(公告)日：2007-02-27
申请号：US10625007
申请日：2003-07-23
申请人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
发明人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.
摘要翻译：提供了一种制造双镶嵌互连的方法。在具有3.3或更小的介电常数的混合电介质层中形成双镶嵌区域，并且使用无碳无机材料作为通孔填料。本发明改进了双镶嵌互连的电性能并使缺陷最小化。

3. 发明授权

US06815331B2 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US06815331B2
公开(公告)日：2004-11-09
申请号：US10392710
申请日：2003-03-20
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L214163
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; forming an interlayer dielectric layer on the stopper layer; forming a hard mask layer on the interlayer dielectric layer; forming a first photoresist pattern on the hard mask layer, the first photoresist pattern having a first opening corresponding to the conductive layer; etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask to form a via hole in the interlayer dielectric layer through which a portion of the stopper layer is exposed; removing the first photoresist pattern; filling the via hole with an intermediary material layer; etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region, wherein the hard mask pattern comprises a second opening that overlaps the entire via hole or at least a portion of the via hole; removing the intermediary material layer from the via hole; forming the wiring region by etching a portion of the interlayer dielectric layer using the hard mask pattern as an etching mask; removing a portion of the stopper layer exposed by the via hole; and filling the via hole and the wiring region with a conductive material.
摘要翻译：使用双镶嵌工艺在半导体器件中形成金属布线层的方法。一方面，在半导体器件中形成金属布线的方法包括：在其上形成有导电层的半导体衬底上形成阻挡层; 在所述阻挡层上形成层间绝缘层; 在所述层间介质层上形成硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂图案，所述第一光致抗蚀剂图案具有对应于所述导电层的第一开口; 使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，以在阻挡层的一部分暴露的层间绝缘层中形成通孔; 去除第一光致抗蚀剂图案; 用中间材料层填充通孔; 蚀刻硬掩模层的一部分以形成限定布线区域的硬掩模图案，其中硬掩模图案包括与整个通孔或通孔的至少一部分重叠的第二开口; 从所述通孔中去除所述中间材料层; 通过使用硬掩模图案作为蚀刻掩模蚀刻层间电介质层的一部分来形成布线区域; 去除由通孔露出的阻挡层的一部分; 以及用导电材料填充所述通孔和所述布线区域。

4. 发明授权

US06861347B2 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US06861347B2
公开(公告)日：2005-03-01
申请号：US10114274
申请日：2002-04-02
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76835
摘要： A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.
摘要翻译：提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。去除第一光致抗蚀剂图案。在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。同时去除第二光致抗蚀剂图案和有机材料层。通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

5. 发明申请

US20050029010A1 Void-free metal interconnection steucture and method of forming the same 有权
标题翻译：无孔金属互连结构及其形成方法
公开(公告)号：US20050029010A1
公开(公告)日：2005-02-10
申请号：US10891062
申请日：2004-07-15
申请人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
发明人： Jeong-hoon Ahn , Hyo-jong Lee , Kyung-tae Lee , Kyoung-woo Lee , Soo-geun Lee , Bong-seok Suh
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L21/4763 , H01L23/52 , H05K1/11
CPC分类号： H01L21/76877 , H01L21/76847
摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.
摘要翻译：金属互连结构包括设置在第一层间电介质层中的下金属互连层。具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

6. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

7. 发明授权

US07041592B2 Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process 失效
标题翻译：使用改进的双镶嵌工艺形成半导体器件的金属互连层的方法
公开(公告)号：US07041592B2
公开(公告)日：2006-05-09
申请号：US10449973
申请日：2003-05-30
申请人： Jae-hak Kim , Soo-geun Lee , Kyung-woo Lee
发明人： Jae-hak Kim , Soo-geun Lee , Kyung-woo Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76877
摘要： A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.
摘要翻译：一种用于形成半导体器件的金属互连层的方法包括在层间绝缘膜上形成包括对灰色处理中使用的介质有选择性的材料的膜。该方法包括在灰化处理期间转换膜以形成具有双镶嵌结构的互连图案。介电材料如铜沉积在互连图案上，其通过CMP平坦化，从而形成具有单个镶嵌结构的通孔接头，而其中没有凹槽。

8. 发明申请

US20070059923A1 Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods 审中-公开
标题翻译：在使用这种方法制造的半导体器件和半导体器件中制造镶嵌互连线的方法
公开(公告)号：US20070059923A1
公开(公告)日：2007-03-15
申请号：US11445458
申请日：2006-06-02
申请人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
发明人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76834 , H01L21/76843
摘要： Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.
摘要翻译：在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽，并填充沟槽以制造连接到通孔的镶嵌互连线。

9. 发明授权

US07605472B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07605472B2
公开(公告)日：2009-10-20
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

10. 发明授权

US07279733B2 Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same 失效
标题翻译：金属绝缘体 - 金属电容器的双镶嵌互连及其制造方法
公开(公告)号：US07279733B2
公开(公告)日：2007-10-09
申请号：US10799292
申请日：2004-03-12
申请人： Kyoung-woo Lee , Soo-geun Lee
发明人： Kyoung-woo Lee , Soo-geun Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/76807 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.
摘要翻译：提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。在该结构中，在通孔级IMD上形成MIM电容器。在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

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