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1. 发明授权

US08571142B1 System and method for non-crystal-based communications 失效
标题翻译：非晶体通信的系统和方法
公开(公告)号：US08571142B1
公开(公告)日：2013-10-29
申请号：US13309464
申请日：2011-12-01
申请人： Songping Wu , Gang Liu , Daxiao Yu , Yonghua Song
发明人： Songping Wu , Gang Liu , Daxiao Yu , Yonghua Song
IPC分类号： H04L27/00 , H03D3/00 , H04W4/00 , H04B7/00 , H04B1/18 , H04B1/28 , H04B15/00
CPC分类号： H04B1/16 , H04L27/0006 , H04W16/14 , H04W56/0035 , H04W72/06 , H04W72/08 , H04W72/085
摘要： Systems and methods for using non-crystal-based reference oscillators in the transmission and reception of frequency-modulated signals are disclosed. To protect against intrusion on neighboring designated frequency bands, guard bands, having a collective width greater than the total expected error based on the contribution of the frequency error from the non-crystal-based oscillators in the transmitter and/or receiver, can be designated. To protect against inter-channel interference within a designated frequency band, transmitters and receivers can include static sub-bandwidths wider than any possible total frequency error, such that it would be impossible for a transmitter or receiver to attempt to communicate on an unintended sub-band. The determination of the total possible frequency error can be determined dynamically based on the correlation between a received training sequence and a known pattern before or a communication session to avoid or correct for frequency offset or drift due to the use of non-crystal-based reference oscillators.
摘要翻译：公开了在频率调制信号的发送和接收中使用基于非晶体的参考振荡器的系统和方法。为了防止侵入相邻的指定频带，可以指定具有大于总预期误差的总宽度的保护频带，其基于来自发射机和/或接收机中的非晶体振荡器的频率误差的贡献，可以指定。为了防止指定频带内的信道间干扰，发射机和接收机可以包括比任何可能的总频率误差更宽的静态子带宽，使得发射机或接收机不可能尝试在非预期子带上进行通信，带。可以基于接收到的训练序列与通信会话之前的已知模式之间的相关性来动态地确定总可能的频率误差，以避免或校正由于使用非基于参考的频率偏移或漂移振荡器。

2. 发明授权

US09184839B1 Method and apparatus for compensating impairments in radio frequency circuitry of a wireless device 有权
标题翻译：用于补偿无线设备的射频电路中的损伤的方法和装置
公开(公告)号：US09184839B1
公开(公告)日：2015-11-10
申请号：US13566157
申请日：2012-08-03
申请人： Songping Wu , Daxiao Yu , Yonghua Song
发明人： Songping Wu , Daxiao Yu , Yonghua Song
IPC分类号： H04B10/2507 , H04B17/20
CPC分类号： H04B17/17
摘要： The present disclosure describes techniques for identity-based RF circuitry compensation. In some aspects data from a wireless device is received via radio frequency circuitry, the data including an identifier that uniquely identifies the wireless device. Impairments of the radio frequency circuitry are estimated based on the received data and then the estimated impairments are associated with the identifier of the wireless device. In response to subsequently receiving data that includes the identifier, the radio frequency circuitry is compensated using the estimated impairments.
摘要翻译：本公开描述了用于基于身份的RF电路补偿的技术。在一些方面，来自无线设备的数据经由射频电路接收，该数据包括唯一地标识无线设备的标识符。基于接收到的数据来估计射频电路的损害，然后估计的损伤与无线设备的标识符相关联。响应于随后接收包括标识符的数据，使用估计的损伤来补偿射频电路。

3. 发明授权

US07664204B1 Adaptive timing using clock recovery 有权
标题翻译：使用时钟恢复的自适应时序
公开(公告)号：US07664204B1
公开(公告)日：2010-02-16
申请号：US11078717
申请日：2005-03-10
申请人： Hui Wang , Yonghua Song
发明人： Hui Wang , Yonghua Song
IPC分类号： H04L27/00 , H03D3/24
CPC分类号： H04L27/0014 , H04L2027/0036 , H04L2027/0053 , H04L2027/0065 , H04L2027/0067 , H04L2027/0091
摘要： Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.
摘要翻译：提供电路和方法，用于在近似主机时钟信号的频率时调整本地时钟信号的频率。锁相环产生具有第一相位和第一频率的本地时钟信号。偏移调整电路接收与输入数据信号相关的本地时钟信号的定时信息，并计算出相应的偏移和指示对本地时钟信号进行调整的频率偏移。第一相位内插器从本地时钟信号产生接收时钟信号，接收时钟信号具有响应于相位和频率偏移的第二相位和第二频率。第二相位插值器响应于频率偏移从具有第三频率的本地时钟信号产生发送时钟信号。

4. 发明授权

US07528657B1 Baseband filter start-up circuit 有权
标题翻译：基带滤波器启动电路
公开(公告)号：US07528657B1
公开(公告)日：2009-05-05
申请号：US11699890
申请日：2007-01-30
申请人： Donghong Cui , Yonghua Song
发明人： Donghong Cui , Yonghua Song
IPC分类号： H03F3/45
CPC分类号： H03F3/45094 , H03F1/34 , H03F3/45475 , H03F3/72 , H03F2203/45521
摘要： An electrical circuit comprises a plurality of amplifiers. Each of the plurality of amplifiers comprises an input circuit in communication with an input of the amplifier and a start-up circuit in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. An output circuit communicates with an output of the amplifier and with the input circuit and the start-up circuit. Respective inputs of a first and a second amplifier of the plurality of amplifiers are in communication with outputs of a third amplifier of the plurality of amplifiers. Outputs of the second amplifier are in communication with inputs of the third amplifier.
摘要翻译：电路包括多个放大器。多个放大器中的每一个包括与放大器的输入通信的输入电路和与输入电路通信的启动电路。启动电路被配置为产生启动信号以使能放大器的后续操作。输出电路与放大器的输出以及输入电路和启动电路进行通信。多个放大器的第一和第二放大器的相应输入端与多个放大器的第三放大器的输出端相通。第二放大器的输出与第三放大器的输入端通信。

5. 发明授权

US07454634B1 Power savings apparatus and method for wireless network devices 有权
标题翻译：无线网络设备的省电设备和方法
公开(公告)号：US07454634B1
公开(公告)日：2008-11-18
申请号：US11070481
申请日：2005-03-02
申请人： Timothy Donovan , Shafiq Jamal , Yonghua Song , Chia-Chun Chung , Tam Tran , Lawrence Tse
发明人： Timothy Donovan , Shafiq Jamal , Yonghua Song , Chia-Chun Chung , Tam Tran , Lawrence Tse
IPC分类号： G06F1/32
CPC分类号： H04W52/029 , Y02D70/142 , Y02D70/22
摘要： A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.
摘要翻译：具有有源和不活动模式的无线网络设备包括产生具有第一时钟速率的第一时钟信号的时钟产生模块。电压供应模块产生小于第一电压电平的第一电压电平和第二电压电平。第一数字模块在活动模式期间接收第一时钟速率和第一电压电平，在非活动模式期间接收第二电压电平，并且在非活动模式期间不接收第一时钟信号。第一模拟模块与电压供应模块通信，并且在非活动模式期间具有减少的电流消耗。

6. 发明授权

US07259600B1 Scalable integrated circuit architecture 有权
标题翻译：可扩展集成电路架构
公开(公告)号：US07259600B1
公开(公告)日：2007-08-21
申请号：US11542978
申请日：2006-10-04
申请人： Yonghua Song
发明人： Yonghua Song
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0805
摘要： An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output signal of the VCO to the reference signal and outputs a drive signal to the control terminal of the master transistor based on the comparison. N slave transistors have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals.
摘要翻译：集成电路架构包括锁相环（PLL）电路，其包括接收参考信号的反馈电路。压控振荡器（VCO）产生到反馈电路的输入端的输出信号。主晶体管具有与VCO通信的控制端子，第一端子和第二端子。反馈电路将VCO的输出信号与参考信号进行比较，并根据比较将驱动信号输出到主晶体管的控制端。 N个从属晶体管具有与主晶体管，第一端子和第二端子的控制端子通信的控制端子。

7. 发明授权

US07190199B1 Scalable integrated circuit architecture with analog circuits 有权
标题翻译：具有模拟电路的可扩展集成电路架构
公开(公告)号：US07190199B1
公开(公告)日：2007-03-13
申请号：US11281756
申请日：2005-11-17
申请人： Yonghua Song
发明人： Yonghua Song
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0805
摘要： An integrated circuit architecture includes a temperature-process tracking circuit that includes a master transistor with a control terminal, a first terminal and a second terminal. The temperature-process tracking circuit generates a drive signal that is output to the control terminal. The integrated circuit architecture includes N analog circuits and N slave transistors, which have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals that communicate with respective ones of the N analog circuits.
摘要翻译：集成电路架构包括温度处理跟踪电路，其包括具有控制端子的主晶体管，第一端子和第二端子。温度过程跟踪电路产生输出到控制端的驱动信号。集成电路架构包括N个模拟电路和N个从属晶体管，其具有与主晶体管的控制端子，第一端子以及与N个模拟电路中的相应模拟电路通信的第二端子进行通信的控制端子。

8. 发明授权

US06998888B1 Scalable integrated circuit architecture with analog circuits 失效
标题翻译：具有模拟电路的可扩展集成电路架构
公开(公告)号：US06998888B1
公开(公告)日：2006-02-14
申请号：US10795039
申请日：2004-03-05
申请人： Yonghua Song
发明人： Yonghua Song
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0805
摘要： An integrated circuit architecture includes a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) has an output that communicates with an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output of the VCO to the reference signal and generates a drive signal that is output to the control terminal of the master transistor. The integrated circuit architecture further includes N analog circuits and N slave transistors that have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals that communicate with respective ones of the N analog circuits.
摘要翻译：集成电路架构包括锁相环（PLL）电路，其包括接收参考信号的反馈电路。压控振荡器（VCO）具有与反馈电路的输入通信的输出。主晶体管具有与VCO通信的控制端子，第一端子和第二端子。反馈电路将VCO的输出与参考信号进行比较，并产生输出到主晶体管的控制端的驱动信号。集成电路架构还包括N个模拟电路和N个从属晶体管，其具有与主晶体管的控制端子，第一端子和与N个模拟电路中的相应模拟电路通信的第二端子进行通信的控制端子。

9. 发明授权

US06359499B1 Temperature and process independent CMOS circuit 有权
标题翻译：温度和工艺独立的CMOS电路
公开(公告)号：US06359499B1
公开(公告)日：2002-03-19
申请号：US09599907
申请日：2000-06-23
申请人： Yonghua Song
发明人： Yonghua Song
IPC分类号： H01L3500
CPC分类号： H03F1/301 , G06G7/12 , H03K19/00384
摘要： A analog function is constructed based on CMOS (complimentary metal-oxide semiconductor) technology. It is capable of providing an output voltage, which is proportional to the product of two input voltages. This analog function is insensitive to temperature and process variations by using a PMOS device as a load device for an NMOS analog function. The PMOS characteristics are used cancel or balance the variations in process and temperature in the other NMOS devices. To further control the function of the loading devices a loading device controller within the analog function compensates for changes in voltage level of the output signal due to variations in temperature and variations in manufacturing process within the function core circuit. The loading device controller has a loading control voltage terminal to provide the loading control voltage to provide temperature and process compensating biasing voltage for the load devices.
摘要翻译：基于CMOS（互补金属氧化物半导体）技术构建模拟功能。它能够提供与两个输入电压的乘积成比例的输出电压。该模拟功能通过使用PMOS器件作为NMOS模拟功能的负载器件，对温度和工艺变化不敏感。使用PMOS特性来消除或平衡其他NMOS器件中的工艺和温度变化。为了进一步控制加载装置的功能，模拟功能内的加载装置控制器补偿由于温度的变化和功能核心电路内的制造过程的变化而导致的输出信号的电压电平的变化。加载装置控制器具有负载控制电压端子，以提供负载控制电压，为负载装置提供温度和工艺补偿偏置电压。

10. 发明授权

US08331206B1 Calibration based DC coupled analog front end for optical storage system 有权
标题翻译：基于校准的直流耦合模拟前端用于光存储系统
公开(公告)号：US08331206B1
公开(公告)日：2012-12-11
申请号：US12972733
申请日：2010-12-20
申请人： Yingxuan Li , Fu-Tai An , Yonghua Song
发明人： Yingxuan Li , Fu-Tai An , Yonghua Song
IPC分类号： G11B7/00
CPC分类号： G11B7/0945
摘要： In an apparatus for conditioning a signal from an optical pickup unit (OPU), a single-ended channel includes a first signal processing block to calibrate a dark level of a single-ended signal corresponding to a single-ended output of the OPU, if any, and to center the single-ended signal. A dual-ended channel includes a second signal processing block to calibrate a dark level of a dual-ended signal corresponding to a dual-ended output of the OPU, if any, and to center the dual-ended signal. A multiplexer selects one of the single-ended channel and the dual-ended channel, and outputs a selected signal. A digital signal processing stage converts the selected signal to a digital signal.
摘要翻译：在用于调节来自光学拾取单元（OPU）的信号的装置中，单端通道包括第一信号处理块，用于校准对应于OPU的单端输出的单端信号的暗电平，如果任何，并将中心的单端信号。双端通道包括第二信号处理块，用于校准对应于OPU的双端输出的双端信号的暗电平（如果有的话），并使双端信号居中。复用器选择单端信道和双端信道之一，并输出所选信号。数字信号处理级将选择的信号转换为数字信号。

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