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1. 发明申请

US20080118717A1 HARDMASK FOR IMPROVED RELIABILITY OF SILICON BASED DIELECTRICS 审中-公开
公开(公告)号：US20080118717A1
公开(公告)日：2008-05-22
申请号：US12018640
申请日：2008-01-23
申请人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
发明人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
IPC分类号： B32B3/00
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3122 , H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

2. 发明申请

US20060091559A1 Hardmask for improved reliability of silicon based dielectrics 有权
公开(公告)号：US20060091559A1
公开(公告)日：2006-05-04
申请号：US10981233
申请日：2004-11-04
申请人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
发明人： Son Nguyen , Michael Lane , Stephen Gates , Xiao Liu , Vincent McGahay , Sanjay Mehta , Thomas Shaw
IPC分类号： H01L21/4763 , H01L23/52 , H01L21/31
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3122 , H01L21/76807 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

3. 发明申请

US20060189133A1 Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 失效
标题翻译：可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP
公开(公告)号：US20060189133A1
公开(公告)日：2006-08-24
申请号：US11063152
申请日：2005-02-22
申请人： Christos Dimitrakopoulos , Stephen Gates , Vincent McGahay , Sanjay Mehta
发明人： Christos Dimitrakopoulos , Stephen Gates , Vincent McGahay , Sanjay Mehta
IPC分类号： H01L21/4763 , H01L21/44 , H01L23/48
CPC分类号： H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
摘要翻译：本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

4. 发明申请

US20070228570A1 RELIABLE BEOL INTEGRATION PROCESS WITH DIRECT CMP OF POROUS SiCOH DIELECTRIC 有权
标题翻译：具有多孔SiCOH介质的直接CMP的可靠的整流过程
公开(公告)号：US20070228570A1
公开(公告)日：2007-10-04
申请号：US11763135
申请日：2007-06-14
申请人： Christos Dimitrakopoulos , Stephen Gates , Vincent McGahay , Sanjay Mehta
发明人： Christos Dimitrakopoulos , Stephen Gates , Vincent McGahay , Sanjay Mehta
IPC分类号： H01L23/532
CPC分类号： H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
摘要翻译：本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

5. 发明申请

US20070072412A1 PREVENTING DAMAGE TO INTERLEVEL DIELECTRIC 审中-公开
标题翻译：防止对交流电介质的损害
公开(公告)号：US20070072412A1
公开(公告)日：2007-03-29
申请号：US11162883
申请日：2005-09-27
申请人： Derren Dunn , Nicholas Fuller , Catherine Labelle , Vincent McGahay , Sanjay Mehta , Henry Nye III
发明人： Derren Dunn , Nicholas Fuller , Catherine Labelle , Vincent McGahay , Sanjay Mehta , Henry Nye III
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/31138 , H01L21/02118 , H01L21/02123 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/31116 , H01L21/31608 , H01L21/76831
摘要： Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.
摘要翻译：通过在ILD中形成开口（例如，沟槽）来提供对层间电介质（ILD）的损坏的防止，并且通过在ILD内或在ILD内过度蚀刻到电介质层中，将电介质膜溅射到开口的侧壁上形成开口。再溅射的膜保护开口的侧壁不受后续的等离子体/灰分过程的影响，并且沿着侧壁和底部密封多孔电介质表面，而不影响整个工艺流程。还公开了由上述方法得到的半导体结构。

6. 发明授权

US08679941B2 Method to improve wet etch budget in FEOL integration 失效
标题翻译：在FEOL集成中改善湿法蚀刻预算的方法
公开(公告)号：US08679941B2
公开(公告)日：2014-03-25
申请号：US13422138
申请日：2012-03-16
申请人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

7. 发明授权

US08617961B1 Post-gate isolation area formation for fin field effect transistor device 有权
标题翻译：鳍状场效应晶体管器件的栅极间隔离区域形成
公开(公告)号：US08617961B1
公开(公告)日：2013-12-31
申请号：US13551659
申请日：2012-07-18
申请人： Balasubramanian S. Haran , Sanjay Mehta , Theodorus E. Standaert
发明人： Balasubramanian S. Haran , Sanjay Mehta , Theodorus E. Standaert
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/823431 , H01L21/845 , H01L29/66545
摘要： A method for fin field effect transistor (finFET) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finFET device after formation of the gate region, wherein forming the isolation areas for the finFET device comprises performing one of oxidation or removal of a subset of the plurality of fins.
摘要翻译：鳍状场效应晶体管（finFET）器件形成的方法包括在衬底上形成多个翅片; 在所述多个翅片上形成栅极区域; 以及在形成栅极区域之后形成用于finFET器件的隔离区域，其中形成用于finFET器件的隔离区域包括执行多个鳍片的子集的氧化或去除之一。

8. 发明申请

US20130292746A1 DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE 审中-公开
公开(公告)号：US20130292746A1
公开(公告)日：2013-11-07
申请号：US13606706
申请日：2012-09-07
申请人： Hemanth Jagannathan , Sanjay Mehta
发明人： Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L29/78
CPC分类号： F04B19/006 , F04B43/0054 , F04B43/043 , F04B45/047
摘要： After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.

9. 发明申请

US20130229005A1 Vehicle Cross-Member Assembly with Adhesive Reservoirs 审中-公开
标题翻译：带有粘性水库的车辆跨部件装配
公开(公告)号：US20130229005A1
公开(公告)日：2013-09-05
申请号：US13682483
申请日：2012-11-20
申请人： John Martin Knittel , Xiaoming Chen , Sanjay Mehta , Michael M. Azzouz , Eric William Barrett , Mark Wlotkowski
发明人： John Martin Knittel , Xiaoming Chen , Sanjay Mehta , Michael M. Azzouz , Eric William Barrett , Mark Wlotkowski
IPC分类号： B62D21/02 , B32B37/12 , B23K31/02
CPC分类号： B62D21/02 , B23K26/28 , B23K31/02 , B23K33/006 , B23K33/008 , B23K2101/006 , B23K2101/185 , B23K2101/28 , B23K2103/04 , B23K2103/08 , B23K2103/10 , B23K2103/14 , B23K2103/15 , B23K2103/16 , B23K2103/172 , B23K2103/18 , B23K2103/20 , B23K2103/42 , B32B37/1284 , Y10T29/49622 , Y10T29/49826 , Y10T29/49956 , Y10T156/1002 , Y10T156/1051
摘要： A method of manufacturing a vehicle cross-member assembly includes: adding adhesive to an adhesive reservoir in an interconnecting member composed of a first material; overlapping a first rail composed of a second material with the interconnecting member; and welding the interconnecting member to a second rail in a position perpendicular with respect to the second rail. The second rail is composed of a different material than the first rail.
摘要翻译：制造车辆横梁组件的方法包括：将粘合剂添加到由第一材料构成的互连构件中的粘合剂储存器; 将由第二材料构成的第一轨道与互连构件重叠; 以及将所述互连构件焊接到相对于所述第二轨道垂直的位置中的第二轨道。第二轨道由与第一轨道不同的材料组成。

10. 发明授权

US08394684B2 Structure and method for stress latching in non-planar semiconductor devices 有权
标题翻译：非平面半导体器件中应力锁定的结构和方法
公开(公告)号：US08394684B2
公开(公告)日：2013-03-12
申请号：US12841408
申请日：2010-07-22
申请人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Sanjay Mehta
发明人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/84
CPC分类号： H01L27/0886 , H01L21/82 , H01L29/66795 , H01L29/7847 , H01L29/785
摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.
摘要翻译：公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落，用各种衬垫封装。形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。在该退火期间，发生错位取向的晶体结构的再结晶。去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。

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