专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6099393A Polishing method for semiconductors and apparatus therefor 失效
标题翻译：半导体抛光方法及其设备
公开(公告)号：US6099393A
公开(公告)日：2000-08-08
申请号：US80728
申请日：1998-05-21
申请人： Soichi Katagiri , Shigeo Moriyama , Kan Yasui , Katsuhiko Yamaguchi
发明人： Soichi Katagiri , Shigeo Moriyama , Kan Yasui , Katsuhiko Yamaguchi
IPC分类号： B24B37/00 , B24B53/007 , B24B53/013 , H01L21/304 , B24B1/00
CPC分类号： B24B53/017 , B24B53/013
摘要： In the polishing machine 10 for pressing the polished surface 7 of the workpiece 1 against the face where there are abrasives 15 of the rotating polishing tool 11 and executing chemical mechanical polishing, the brushing device 30, the cleaner 40, the abrasive supplier 52, and the pure water supplier 60 are sequentially arranged behind the location of the head 20 for pressing the workpiece 1 against the polishing tool 11 in the rotational direction. The cleaner 40 sprays the cleaning water 47 to the face where there are abrasives 15 of the rotating polishing tool 11 and sucks and collects it by the vacuum hole 45. Fresh slurry 62 is always supplied by the slurry supplier 63 comprising the abrasive supplier 52 and the pure water supplier 60.
摘要翻译：在用于将工件1的抛光表面7压靠在旋转抛光工具11的磨料15的表面上并执行化学机械抛光的抛光机10中，刷洗装置30，清洁器40，磨料供应器52和纯水供应器60顺序地布置在头部20的位置之后，用于将工件1沿着旋转方向压靠在抛光工具11上。清洁器40将清洗水47喷射到旋转研磨工具11的磨料15的表面，并通过真空孔45吸收并收集。新鲜浆料62总是由包含磨料供应器52的浆料供给器63供应，纯水供应商60。

2. 发明授权

US07137866B2 Polishing apparatus and method for producing semiconductors using the apparatus 有权
公开(公告)号：US07137866B2
公开(公告)日：2006-11-21
申请号：US11267306
申请日：2005-11-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B49/00
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/02 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended.Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate.The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

3. 发明申请

US20050095960A1 Polishing apparatus and method for producing semiconductors using the apparatus 有权
标题翻译：抛光装置及其制造方法
公开(公告)号：US20050095960A1
公开(公告)日：2005-05-05
申请号：US11004991
申请日：2004-12-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B37/04 , B24B41/04 , B24B53/12 , B24B49/00 , B24B1/00
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.
摘要翻译：本发明涉及一种抛光装置以及使用该装置的半导体制造方法。磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度，并且可以总是执行具有较少的面内不均匀性的处理。因此，修整工具的寿命可以大大延长。此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。

4. 发明授权

US07166013B2 Polishing apparatus and method for producing semiconductors using the apparatus 有权
标题翻译：抛光装置及其制造方法
公开(公告)号：US07166013B2
公开(公告)日：2007-01-23
申请号：US11004991
申请日：2004-12-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B49/00 , B24B51/00 , B24B1/00 , B24B29/00
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended.Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate.The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.
摘要翻译：本发明涉及一种抛光装置以及使用该装置的半导体制造方法。磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度，并且可以总是执行具有较少的面内不均匀性的处理。因此，修整工具的寿命可以大大延长。此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。

5. 发明申请

US20060057940A1 Polishing apparatus and method for producing semiconductors using the apparatus 有权
公开(公告)号：US20060057940A1
公开(公告)日：2006-03-16
申请号：US11267306
申请日：2005-11-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B51/00 , B24B7/30 , B24B1/00 , B24B29/00 , B24B21/18
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/02 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

6. 发明授权

US06221773B1 Method for working semiconductor wafer 有权
标题翻译：半导体晶圆工作方法
公开(公告)号：US06221773B1
公开(公告)日：2001-04-24
申请号：US09254431
申请日：1999-03-09
申请人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
发明人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , B24B7/228 , B24B37/04 , B24B37/042 , B24B37/08 , B24B53/017 , Y10S438/959
摘要： A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.
摘要翻译：一种用于处理半导体晶片的方法，其在工作表面的直径大于所述半导体的直径的区域内，以半导体晶片形成在半导体晶片上，通过处理具有不平坦表面的膜，以良好可控的方式并且以高精度提供平坦化表面晶片不超过两次，并且通过用设置在垂直布置的工作表面上的供应单元供应的抛光液处理该膜。此外，通过工作表面的较小直径，可以容易地进行工作表面的高质量的修整。此外，工作表面的垂直布置使得可以准确地兼容扩大直径的半导体晶片。

7. 发明授权

US06676496B2 Apparatus for processing semiconductor wafers 失效
标题翻译：半导体晶圆处理装置
公开(公告)号：US06676496B2
公开(公告)日：2004-01-13
申请号：US09835359
申请日：2001-04-17
申请人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
发明人： Kan Yasui , Shigeo Moriyama , Katsuhiko Yamaguchi , Yoshio Homma
IPC分类号： B24B100
CPC分类号： B24B37/04 , B24B57/02
摘要： A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.
摘要翻译：一种用于处理半导体晶片的方法，其在工作表面的直径大于所述半导体的直径的区域内，以半导体晶片形成在半导体晶片上，通过处理具有不平坦表面的膜，以良好可控的方式并且以高精度提供平坦化表面晶片不超过两次，并且通过用设置在垂直布置的工作表面上的供应单元供应的抛光液处理该膜。此外，通过工作表面的较小直径，可以容易地进行工作表面的高质量的修整。此外，工作表面的垂直布置使得可以准确地兼容扩大直径的半导体晶片。

8. 发明授权

US5408320A Workpiece having alignment marks for positioning a pattern at a different pitch to be formed thereon, and method for fabricating the same 失效
标题翻译：具有用于定位在其上形成的不同间距的图案的对准标记的工件及其制造方法
公开(公告)号：US5408320A
公开(公告)日：1995-04-18
申请号：US994963
申请日：1992-12-22
申请人： Soichi Katagiri , Shigeo Moriyama , Tsuneo Terasawa , Masaaki Itou
发明人： Soichi Katagiri , Shigeo Moriyama , Tsuneo Terasawa , Masaaki Itou
IPC分类号： G01B11/27 , G01D5/30 , G03F9/00 , G01B9/02
CPC分类号： G03F9/7084 , G01B11/272 , G01D5/30 , G03F9/70
摘要： A semiconductor wafer includes a top surface on which a semiconductor circuit pattern is to be fabricated, and a bottom surface on which alignment marks for positioning the semiconductor circuit pattern are arranged. The alignment marks are arranged at a predetermined pitch and in an arrangement that is not unique to the pattern formed on the top surface.
摘要翻译：半导体晶片包括其上要制造半导体电路图案的顶表面和布置有用于定位半导体电路图案的对准标记的底表面。对准标记以预定的间距布置，并且以对于形成在顶表面上的图案不是唯一的布置来布置。

9. 发明授权

US5200798A Method of position detection and the method and apparatus of printing patterns by use of the position detection method 失效
标题翻译：位置检测方法以及使用位置检测方法打印图案的方法和装置
公开(公告)号：US5200798A
公开(公告)日：1993-04-06
申请号：US734159
申请日：1991-07-22
申请人： Soichi Katagiri , Shigeo Moriyama , Tsuneo Terasawa , Masaaki Itou
发明人： Soichi Katagiri , Shigeo Moriyama , Tsuneo Terasawa , Masaaki Itou
IPC分类号： G01B11/27 , G01D5/30 , G03F9/00
CPC分类号： G03F9/7084 , G01B11/272 , G01D5/30 , G03F9/70
摘要： A method for detecting position detection marks on the bottom surface of a sample substrate and for determining the pattern forming positions on the top surface of the sample on the basis of the detected mark positions makes it possible to virtually eliminate the measurement errors caused by sample tilt in the position measurements regarding the sample top surface. When the sample tilts, a positional difference occurs between the top and bottom surfaces of the sample, and errors are accordingly generated in the position measurements from the sample top surface. According to the invention, the mark position measurements from the sample bottom surface are made to contain a deviation that varies with the tilt angle of the sample. The deviation is used to cancel the errors in the measured positions.
摘要翻译：基于检测到的标记位置，检测样品基板的底面上的位置检测标记和样品的上表面上的图案形成位置的方法能够实际上消除样品倾斜引起的测量误差在关于样品顶面的位置测量中。当样品倾斜时，在样品的顶表面和底表面之间发生位置差异，并且因此在从样品顶表面的位置测量中产生误差。根据本发明，使来自样品底表面的标记位置测量值包含随样品的倾斜角度而变化的偏差。偏差用于消除测量位置的误差。

10. 发明授权

US06612912B2 Method for fabricating semiconductor device and processing apparatus for processing semiconductor device 失效
标题翻译：半导体装置的制造方法以及半导体装置的处理装置
公开(公告)号：US06612912B2
公开(公告)日：2003-09-02
申请号：US09371003
申请日：1999-08-10
申请人： Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
发明人： Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
IPC分类号： B24B100
CPC分类号： B24B53/017 , B24B1/04 , B24B37/042 , B24B53/12
摘要： A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
摘要翻译：一种制造半导体器件的方法包括：当半导体晶片的凹凸图案通过使用由晶片保持器保持的半导体晶片进行平面化而进行的刷子或超声波的磨石表面激活处理，磨料颗粒和用于保持磨料颗粒的材料，半导体晶片被相对运动地压在其上。半导体晶片以高去除率进行处理，并且精确地控制抛光厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式