专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5709755A Method for CMP cleaning improvement 失效
标题翻译： CMP清洗改进方法
公开(公告)号：US5709755A
公开(公告)日：1998-01-20
申请号：US694728
申请日：1996-08-09
申请人： So Wein Kuo , Tsu Shih , Chung-Long Chang
发明人： So Wein Kuo , Tsu Shih , Chung-Long Chang
IPC分类号： B08B1/04 , H01L21/00 , H01L21/304 , H01L21/306 , H01L21/30
CPC分类号： H01L21/02052 , B08B1/04 , H01L21/02024 , H01L21/67046
摘要： Using an APM solution to clean both the front and backside of a semiconductor wafer significantly reduces the residue from chemical mechanical polishing. A low residue count holds the wafer more securely to the electrostatic chuck, thus improving processing, reducing wear on the electrostatic chuck, and increasing its lifetime.
摘要翻译：使用APM解决方案清洁半导体晶片的正面和背面显着减少化学机械抛光的残留物。低残留数量将晶片更牢固地保持在静电卡盘上，从而改善处理，减少静电卡盘上的磨损，并延长其使用寿命。

2. 发明授权

US5661084A Method for contact profile improvement 失效
标题翻译：联系方式改进方法
公开(公告)号：US5661084A
公开(公告)日：1997-08-26
申请号：US725808
申请日：1996-10-04
申请人： So Wein Kuo , Tsu Shih
发明人： So Wein Kuo , Tsu Shih
IPC分类号： H01L21/311 , H01L21/283 , H01L21/31
CPC分类号： H01L21/31144
摘要： A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening. The substrate is dipped into a hydrofluoric acid solution to remove the native oxide on the sidewalls of the contact opening whereby the hydrofluoric acid etches the BPTEOS layer at a slower rate than it etches the first and third TEOS layers whereby the contact profile is made vertical. A glue layer is sputter deposited over the surface of the insulating layer structure and within the contact opening. A conducting layer is deposited over the glue layer filling the contact opening completing the electrical contact in the fabrication of the integrated circuit device.
摘要翻译：描述了一种用于制造用于CMOS或其他集成电路的接触或通孔开口和填充冶金的方法。半导体器件结构设置在半导体衬底中和半导体衬底上。在其上形成绝缘层结构，其中包括第一层四乙氧基硅烷（TEOS），第二层硼磷-POOS（BPTEOS）和第三层TEOS。通过未被掩模覆盖的绝缘层结构蚀刻接触开口到要电接触的半导体器件结构，其中由于BPTEOS层被蚀刻，接触开口的轮廓不垂直。水平地多于第一和第三TEOS层，并且其中天然氧化物积聚在接触开口的侧壁上。将基底浸入氢氟酸溶液中以除去接触开口侧壁上的天然氧化物，由此氢氟酸以比蚀刻第一和第三TEOS层更慢的速率蚀刻BPTEOS层，从而使接触轮廓垂直。在绝缘层结构的表面上和接触开口内溅射沉积胶层。在集成电路器件的制造中，导电层沉积在填充接触开口的胶层上，完成电接触。

3. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

4. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

5. 发明授权

US5933744A Alignment method for used in chemical mechanical polishing process 失效
标题翻译：用于化学机械抛光工艺的对准方法
公开(公告)号：US5933744A
公开(公告)日：1999-08-03
申请号：US54302
申请日：1998-04-02
申请人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
发明人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
IPC分类号： H01L21/3105 , H01L23/544 , H01L21/465 , H01L21/76
CPC分类号： H01L23/544 , H01L21/31053 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.
摘要翻译：用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。第一介电层沉积在晶片上用于隔离。然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。在第一电介质层中形成第一导电插塞。接下来，在第一电介质层的表面和钨插塞上形成第一导电层。因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

6. 发明授权

US06686284B2 Chemical mechanical polisher equipped with chilled retaining ring and method of using 失效
标题翻译：化学机械抛光机配有冷冻保持环和使用方法
公开(公告)号：US06686284B2
公开(公告)日：2004-02-03
申请号：US10072244
申请日：2002-02-06
申请人： Chi-Wei Chung , Tung-Ching Tseng , Tsu Shih , Syun-Ming Jang
发明人： Chi-Wei Chung , Tung-Ching Tseng , Tsu Shih , Syun-Ming Jang
IPC分类号： H01L2100
CPC分类号： H01L21/3212 , B24B37/32 , B24B55/02 , H01L21/31053
摘要： A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.
摘要翻译：描述了配备有冷冻保持环的化学机械抛光装置和使用该装置的方法。保持环安装有诸如金属管的传热装置，并在其中流过用于从安装在保持环中的晶片携带热量的热交换流体，导致与晶片接触的浆液中的温度降低。因此，本发明的装置和方法减少了抛光期间低k电介质材料和晶片划伤问题的分层问题。

7. 发明授权

US06638868B1 Method for preventing or reducing anodic Cu corrosion during CMP 有权
标题翻译：在CMP期间防止或减少阳极Cu腐蚀的方法
公开(公告)号：US06638868B1
公开(公告)日：2003-10-28
申请号：US10141221
申请日：2002-05-07
申请人： Tsu Shih , Kun Ku Hung , Wen-Hun Tung , Wen-Chin Chiou
发明人： Tsu Shih , Kun Ku Hung , Wen-Hun Tung , Wen-Chin Chiou
IPC分类号： H01L21302
CPC分类号： B24B37/046 , B24B37/042 , H01L21/02071 , H01L21/3212 , H01L21/7684
摘要： A method and apparatus for implementing the method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process the method providing at least one semiconductor wafer polishing surface including copper filled anisotropically etched features; polishing the at least one semiconductor wafer polishing surface according to a CMP process having a polishing pad surface contacting the at least one it semiconductor wafer polishing surface at least a portion of the polishing pad in electrically conductive communication with a conductive polishing platen; and, providing at least one electrically conductive pathway from the conductive polishing platen.
摘要翻译：一种用于在化学机械抛光（CMP）工艺中实现用于防止或减少包含在半导体晶片中的含铜特征的腐蚀的方法和装置，该方法提供至少一个包括铜填充的各向异性蚀刻特征的半导体晶片抛光表面的方法; 根据CMP工艺抛光所述至少一个半导体晶片抛光表面，所述CMP工艺具有抛光垫表面，所述抛光垫表面与所述至少一个半导体晶片抛光表面接触，所述至少一部分所述抛光垫与导电抛光平台导电连通; 以及从所述导电抛光平台提供至少一个导电通路。

8. 发明授权

US06620034B2 Way to remove Cu line damage after Cu CMP 有权
标题翻译： Cu CMP后去除Cu线损伤的方法
公开(公告)号：US06620034B2
公开(公告)日：2003-09-16
申请号：US10043780
申请日：2002-01-14
申请人： Tsu Shih , Jih-Churng Jwu , Ying-Ho Chen , Syun-Ming Jang
发明人： Tsu Shih , Jih-Churng Jwu , Ying-Ho Chen , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/12 , B24B37/015 , B24B55/02
摘要： The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.
摘要翻译：本发明提供了一种方法和装置，其通过在低温下进行CMP工艺，并且通过添加用作腐蚀抑制剂的浆料在CMP工艺期间保持该低温来防止铜线的CMP中的铜离子的累积。

9. 发明授权

US06602780B2 Method for protecting sidewalls of etched openings to prevent via poisoning 有权
标题翻译：用于保护蚀刻开口的侧壁以防止通过中毒的方法
公开(公告)号：US06602780B2
公开(公告)日：2003-08-05
申请号：US09947788
申请日：2001-09-06
申请人： Tsu Shih , Yung-Cheng Lu , Lih Ping Li , Tien-I Bao , Chung Chi Ko
发明人： Tsu Shih , Yung-Cheng Lu , Lih Ping Li , Tien-I Bao , Chung Chi Ko
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76831 , H01L2221/1057
摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.
摘要翻译：一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。

10. 发明授权

US06372632B1 Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer 有权
标题翻译：通过使用牺牲氧化物层来消除铜互连的凹陷的方法
公开(公告)号：US06372632B1
公开(公告)日：2002-04-16
申请号：US09490138
申请日：2000-01-24
申请人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
发明人： Chen-Hua Yu , Weng Chang , Jih-Chung Twu , Tsu Shih
IPC分类号： H01L214763
CPC分类号： H01L21/7688 , H01L21/31053 , H01L21/3212 , H01L21/7684
摘要： A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.
摘要翻译：一种形成平面化金属互连的方法，包括以下步骤。提供半导体结构。在半导体结构上形成低K电介质层。在低K电介质层上形成牺牲层。将牺牲层和低K电介质层图案化以在牺牲层和低K电介质层内形成沟槽。在牺牲层上形成阻挡层，衬在沟槽侧壁和底部。金属沉积在阻挡层上以形成填充衬里沟槽的金属层，并覆盖填充覆盖低K电介质层的牺牲层。金属层和阻挡层被平坦化，暴露牺牲层的上表面。去除牺牲层以形成平坦化的金属互连。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式