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1. 发明授权

US07671456B2 Power management integrated circuit 有权
公开(公告)号：US07671456B2
公开(公告)日：2010-03-02
申请号：US11825252
申请日：2007-07-03
申请人： Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495 , H01L23/52
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

2. 发明授权

US07247930B2 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US07247930B2
公开(公告)日：2007-07-24
申请号：US10955383
申请日：2004-09-30
申请人： Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschantz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电源管理裸片。

3. 发明申请

US20100115301A1 CPU POWER DELIVERY SYSTEM 审中-公开
标题翻译： CPU电源传输系统
公开(公告)号：US20100115301A1
公开(公告)日：2010-05-06
申请号：US12684257
申请日：2010-01-08
申请人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。

4. 发明申请

US20100219516A1 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

5. 发明授权

US08288846B2 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US08288846B2
公开(公告)日：2012-10-16
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495 , H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

6. 发明授权

US07698576B2 CPU power delivery system 有权
标题翻译： CPU供电系统
公开(公告)号：US07698576B2
公开(公告)日：2010-04-13
申请号：US10955746
申请日：2004-09-30
申请人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。

7. 发明申请

US20140089687A1 POWER MANAGEMENT INTEGRATED CIRCUIT 审中-公开
标题翻译：电源管理集成电路
公开(公告)号：US20140089687A1
公开(公告)日：2014-03-27
申请号：US13626357
申请日：2012-09-25
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , H01L23/34 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

8. 发明授权

US4989170A Hybrid stochastic gradient for convergence of adaptive filter 失效
标题翻译：用于自适应滤波器收敛的混合随机梯度
公开(公告)号：US4989170A
公开(公告)日：1991-01-29
申请号：US478719
申请日：1990-02-08
申请人： Roy G. Batruni , Howard A. Wilson
发明人： Roy G. Batruni , Howard A. Wilson
IPC分类号： H03H21/00
CPC分类号： H03H21/0043 , H04L2025/03687 , H04L2025/037 , H04L25/023
摘要： The present invention provides a technique for updating the coefficients a(n) of an adaptive filter impulse response A(n), whereA'(n)=(a.sub.o (n) a.sub.l (n) . . . a.sub.m (n))is the adaptive filter impulse response at time n. The impulse response is utilized for tracking the output y(n) of a communications channel, where ##EQU1## where H is an unknown impulse response of the channel,H'=(h.sub.o h.sub.l . . . h.sub.m),the ' character denoting transposition. The channel is driven with a known input signal s(n), whereS'(n)=(s(n) s(n-l) . . . s(n-m)).According to the techinque, the output x(n) of an adaptive filter, wherex(n)=S'(n)A(n)is compared with the channel output y(n) according to the Least Mean Squares (LMS) algorithm to develop an LMS error prediction signal. At the same time, the adaptive filter output x(n) is compared with the channel output y(n) according to the Sign Algorithm (SA) to develop an SA error prediction signal. If the LMS error signal is greater than or equal to a preselected value, then it is used to update the coefficients a(n) of the adaptive filter impulse response. If the LMS error signal is less than the preselected value, then the SA error signal is used to update the coefficients a(n).
摘要翻译：本发明提供一种用于更新自适应滤波器脉冲响应A（n）的系数a（n）的技术，其中A'（n）=（ao（n）al（n）... am（n））是时间n的自适应滤波器脉冲响应。脉冲响应用于跟踪通信信道的输出y（n），其中其中H是信道的未知脉冲响应，H'=（hohl ...），“表示转置的字符”。信道由已知的输入信号s（n）驱动，其中S'（n）=（s（n）s（n-1）... s（n-m））。根据技术，根据最小二乘法（LMS）将自适应滤波器的输出x（n）与通道输出y（n）进行比较，其中x（n）= S'（n）A（n）算法来开发LMS误差预测信号。同时，根据符号算法（SA）将自适应滤波器输出x（n）与信道输出y（n）进行比较，以形成SA误差预测信号。如果LMS误差信号大于或等于预选值，则用于更新自适应滤波器脉冲响应的系数a（n）。如果LMS误差信号小于预选值，则使用SA误差信号来更新系数a（n）。

9. 发明授权

US07782887B2 Method and apparatus for driving data packets 有权
标题翻译：用于驱动数据包的方法和装置
公开(公告)号：US07782887B2
公开(公告)日：2010-08-24
申请号：US11055243
申请日：2005-02-08
申请人： Sriram R. Vangal , Howard A. Wilson
发明人： Sriram R. Vangal , Howard A. Wilson
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L12/10 , H04L45/12 , H04L45/60
摘要： An apparatus for driver power and size selection includes in one embodiment a controller for controlling the enabling and disabling of legs in a legged driver, the legged driver providing only that amount of power necessary to transfer a data packet from its current location to its destination location. A method of forwarding data packets includes determining the distance between a current location of a data packet and the destination location of the data packet, and enabling as many legs of a legged driver as are necessary to power the transfer of the data packet to its destination.
摘要翻译：用于驱动器功率和尺寸选择的装置包括在一个实施例中的控制器，用于控制腿式驱动器中的腿的启用和禁用，该腿式驱动器仅提供将数据分组从其当前位置传送到其目的地位置所需的功率量。转发数据分组的方法包括确定数据分组的当前位置与数据分组的目的地位置之间的距离，以及使数据分组传送到其目的地所需的足够多的腿式驱动程序。

10. 发明授权

US4926472A Reduction of signal processing requirements in a 2B1Q-code echo canceller or equalizer 失效
标题翻译：减少2B1Q码回波消除器或均衡器中的信号处理要求
公开(公告)号：US4926472A
公开(公告)日：1990-05-15
申请号：US269670
申请日：1988-11-10
申请人： Roy G. Batruni , Howard A. Wilson
发明人： Roy G. Batruni , Howard A. Wilson
IPC分类号： H03H15/00 , H04B3/23 , H04L25/03
CPC分类号： H04L25/03057 , H04B3/235 , H04L25/03038 , H04L25/03133 , H04B3/238
摘要： The present invention provides a technique for data detection signal processing for removing echo interference and/or distortion from a received 2B1Q coded signal. According to the preferred technique, the received 2B1Q signal Q, where q=(-3, -1, +1, +3), is shifted one bit to the left to generate a corresponding shifted symbol alphabet S, where S=(-2, 0, +2, +4). The shifted received signals are then processed through a transversal filter. That is, the signal is provided to a delay line which is tapped at intervals corresponding to the symbol width of the received signal. Each tap along the delay line is connected through an amplifier to a summing device that provides an output y(n), where ##EQU1## The tap gains, or coefficients a.sub.j, are set to subtract the effects of interference from symbols that are adjacent in time to the desired symbol. In an adaptive embodiment of the invention, the output y(n) resulting from the convolution between the transmitted symbols s(n) and the gain coefficients a.sub.j. The output of the transmission channel and the filter output y(n) are then processed in accordance with a convergence algorithm to develop an error feedback signal which is used to update the gain coefficients a.sub.j.

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