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1. 发明授权

US06853644B1 Method and apparatus for driving data packets 失效
公开(公告)号：US06853644B1
公开(公告)日：2005-02-08
申请号：US09470080
申请日：1999-12-22
申请人： Sriram R. Vangal , Howard A. Wilson
发明人： Sriram R. Vangal , Howard A. Wilson
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L12/10 , H04L45/12 , H04L45/60
摘要： An apparatus for driver power and size selection includes in one embodiment a controller for controlling the enabling and disabling of legs in a legged driver, the legged driver providing only that amount of power necessary to transfer a data packet from its current location to its destination location. A method of forwarding data packets includes determining the distance between a current location of a data packet and the destination location of the data packet, and enabling as many legs of a legged driver as are necessary to power the transfer of the data packet to its destination.

2. 发明授权

US07782887B2 Method and apparatus for driving data packets 有权
标题翻译：用于驱动数据包的方法和装置
公开(公告)号：US07782887B2
公开(公告)日：2010-08-24
申请号：US11055243
申请日：2005-02-08
申请人： Sriram R. Vangal , Howard A. Wilson
发明人： Sriram R. Vangal , Howard A. Wilson
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L12/10 , H04L45/12 , H04L45/60
摘要： An apparatus for driver power and size selection includes in one embodiment a controller for controlling the enabling and disabling of legs in a legged driver, the legged driver providing only that amount of power necessary to transfer a data packet from its current location to its destination location. A method of forwarding data packets includes determining the distance between a current location of a data packet and the destination location of the data packet, and enabling as many legs of a legged driver as are necessary to power the transfer of the data packet to its destination.
摘要翻译：用于驱动器功率和尺寸选择的装置包括在一个实施例中的控制器，用于控制腿式驱动器中的腿的启用和禁用，该腿式驱动器仅提供将数据分组从其当前位置传送到其目的地位置所需的功率量。转发数据分组的方法包括确定数据分组的当前位置与数据分组的目的地位置之间的距离，以及使数据分组传送到其目的地所需的足够多的腿式驱动程序。

3. 发明申请

US20090300292A1 Using criticality information to route cache coherency communications 有权
标题翻译：使用关键性信息来路由缓存一致性通信
公开(公告)号：US20090300292A1
公开(公告)日：2009-12-03
申请号：US12156343
申请日：2008-05-30
申请人： Zhen Fang , Liqun Cheng , Sriram R. Vangal
发明人： Zhen Fang , Liqun Cheng , Sriram R. Vangal
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： In one embodiment, the present invention includes a method for receiving a cache coherency message in an interconnect router from a caching agent, mapping the message to a criticality level according to a predetermined mapping, and appending the criticality level to each flow control unit of the message, which can be transmitted from the interconnect router based at least in part on the criticality level. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从高速缓存代理器接收互连路由器中的高速缓存一致性消息的方法，用于根据预定映射将消息映射到临界级，并将关键性级别附加到每个流控制单元消息，其可以至少部分地基于关键性级别从互连路由器发送。描述和要求保护其他实施例。

4. 发明授权

US07181544B2 Network protocol engine 有权
标题翻译：网络协议引擎
公开(公告)号：US07181544B2
公开(公告)日：2007-02-20
申请号：US10234492
申请日：2002-09-03
申请人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
发明人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
IPC分类号： G06F15/16
CPC分类号： H04L69/22 , H04L69/10 , H04L69/12
摘要： Packet processing techniques that can be used, for example, by a network protocol off-load engine. For example, the techniques may be used in an engine that performs transmission control protocol (TCP) operations for received packets for a host.
摘要翻译：可以使用例如由网络协议卸载引擎使用的分组处理技术。例如，这些技术可以用于为主机的接收分组执行传输控制协议（TCP）操作的引擎中。

5. 发明授权

US07080111B2 Floating point multiply accumulator 失效
公开(公告)号：US07080111B2
公开(公告)日：2006-07-18
申请号：US09873557
申请日：2001-06-04
申请人： Amaresh Pangal , Dinesh Somasekhar , Shekhar Y. Borkar , Sriram R. Vangal
发明人： Amaresh Pangal , Dinesh Somasekhar , Shekhar Y. Borkar , Sriram R. Vangal
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936
摘要： A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

6. 发明授权

US06865134B2 Charge recycling decoder, method, and system 失效
标题翻译：充电回收解码器，方法和系统
公开(公告)号：US06865134B2
公开(公告)日：2005-03-08
申请号：US10610490
申请日：2003-06-30
申请人： Sriram R. Vangal , Nitin Y. Borkar
发明人： Sriram R. Vangal , Nitin Y. Borkar
IPC分类号： G11C8/10 , G11C7/00
CPC分类号： G11C8/10
摘要： A charge recycling decoder shares charge between output nodes when input nodes change state.
摘要翻译：当输入节点改变状态时，电荷回收解码器在输出节点之间共享电荷。

7. 发明授权

US06459316B1 Flip flop circuit 失效
标题翻译：触发电路
公开(公告)号：US06459316B1
公开(公告)日：2002-10-01
申请号：US09733216
申请日：2000-12-08
申请人： Sriram R. Vangal , Dinesh Somasekhar
发明人： Sriram R. Vangal , Dinesh Somasekhar
IPC分类号： H03K3289
CPC分类号： H03K3/0372 , H03K3/356121
摘要： A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.
摘要翻译：具有互补输出的双轨触发器包括具有嵌入式逻辑的主级，感测级和一个或多个从动级。触发器工作在预充电状态和评估状态。在时钟信号为低电平的预充电状态期间，触发器将内部保持器节点预充电到高电平。当时钟信号变为高电平时，触发器进入评估状态，并且内部保持器节点之一评估为低值。感觉阶段感知内部维护者节点评估为零，并将其驱动到零更快。从站阶段在评估状态期间反映内部守门员节点的状态，并在预充电状态期间维持其状态。

8. 发明授权

US09337952B2 Embedded resilient buffer 有权
标题翻译：嵌入式弹性缓冲区
公开(公告)号：US09337952B2
公开(公告)日：2016-05-10
申请号：US13867968
申请日：2013-04-22
申请人： Somnath Paul , Sriram R. Vangal
发明人： Somnath Paul , Sriram R. Vangal
IPC分类号： H04L1/00 , H03K19/00 , G06F11/26 , G11C29/00 , G11C29/02 , G06F13/16 , H04L12/70
CPC分类号： G06F11/0787 , G06F5/065 , G06F11/0757 , G06F11/0772 , G06F11/1407 , G06F11/1645 , G06F11/26 , G06F13/1673 , G06F13/1689 , G06F2205/067 , G11C29/003 , G11C29/023 , G11C29/028 , H03K19/00 , H04L1/00 , H04L2012/5681 , Y02D10/14
摘要： Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.
摘要翻译：描述了一种装置，包括：第一顺序单元; 与第一顺序单元并联耦合的第一队列，使得第一队列和第一顺序单元接收第一输入，用于对第一输入进行双倍采样的第一序列; 比较单元，用于接收来自第一顺序单元的输出; 以及由前一周期的写指针控制的第一选择单元，所述第一选择单元接收所述第一队列的每个存储单元的输出，其中所述第一选择单元生成用于由所述第一比较单元进行比较的输出。

9. 发明授权

US09063730B2 Performing variation-aware profiling and dynamic core allocation for a many-core processor 有权
标题翻译：为多核处理器执行变化感知分析和动态核心分配
公开(公告)号：US09063730B2
公开(公告)日：2015-06-23
申请号：US12972985
申请日：2010-12-20
申请人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
发明人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3206 , G06F1/329 , G06F9/4893 , Y02D10/24
摘要： In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核心的处理器，每个核心具有自检电路，以确定相应核心的频率分布和泄漏功率分布。反过来，调度器被耦合以接收频率分布和泄漏功率分布，并且基于频率分布和泄漏功率分布来在至少一些核上调度应用。描述和要求保护其他实施例。

10. 发明授权

US07016354B2 Packet-based clock signal 失效
标题翻译：基于分组的时钟信号
公开(公告)号：US07016354B2
公开(公告)日：2006-03-21
申请号：US10234489
申请日：2002-09-03
申请人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
发明人： Sriram R. Vangal , Yatin Hoskote , Nitin Y. Borkar , Jianping Xu , Vasantha K. Erraguntla , Shekhar Y. Borkar
IPC分类号： H04L12/56
CPC分类号： H04L69/16 , H04J3/0688 , H04L69/161 , H04L69/22
摘要： In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provide to processing logic that processes the at least one packet.
摘要翻译：一般来说，一方面，本公开描述了一种在分组处理中使用的方法。该方法可以包括接收至少一个分组的至少一部分，并且基于至少一个分组的至少一部分，确定时钟信号以提供处理至少一个分组的处理逻辑。

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