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1. 发明授权

US07324379B2 Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line 有权
标题翻译：存储器件和操作方法与高压电源线上的高噪声抑制相同
公开(公告)号：US07324379B2
公开(公告)日：2008-01-29
申请号：US11241729
申请日：2005-09-30
申请人： Nicola Del Gatto , Massimiliano Mollichelli , Massimiliano Scotti , Marco Sforzin
发明人： Nicola Del Gatto , Massimiliano Mollichelli , Massimiliano Scotti , Marco Sforzin
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/24 , G11C16/30
摘要： A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
摘要翻译：存储器件具有存储器单元阵列。列解码器被配置为寻址存储器单元。电荷泵供应电路为列解码器产生升压的电源电压。连接级布置在电源电路和列解码器之间。连接级在高阻抗状态和低阻抗状态之间切换，并且被配置为在存储器件的给定操作条件下，特别是在读取步骤期间切换到高阻抗状态。

2. 发明授权

US06956787B2 Method and device for timing random reading of a memory device 失效
标题翻译：用于定时随机读取存储器件的方法和装置
公开(公告)号：US06956787B2
公开(公告)日：2005-10-18
申请号：US10700322
申请日：2003-11-03
申请人： Carlo Lisi , Marco Ferrario , Massimiliano Scotti , Emanuele Confalonieri
发明人： Carlo Lisi , Marco Ferrario , Massimiliano Scotti , Emanuele Confalonieri
IPC分类号： G11C7/08 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22 , G11C7/04
摘要： A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.
摘要翻译：一种用于定时随机读取具有数据访问时间的存储器件的装置，其中通过一系列连续操作执行读取，所述定时装置被设计为针对每个操作产生相应的定时信号，例如导致任何存储器件的操作条件，相应的操作持续一段等于相应的固定持续时间的时间，其被确定为保证在固定持续时间内完成存储器件的最差工作状态下的操作; 固定持续时间的总和等于存储器件的数据访问时间。

3. 发明授权

US07596023B2 Memory device employing three-level cells and related methods of managing 有权
标题翻译：采用三层单元的存储器件及相关的管理方法
公开(公告)号：US07596023B2
公开(公告)日：2009-09-29
申请号：US11934144
申请日：2007-11-02
申请人： Alessandro Magnavacca , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
发明人： Alessandro Magnavacca , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/3427
摘要： A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
摘要翻译：存储器件可以包括可寻址的三电平单元的阵列，编码电路以三比特串输入，并且基于代码产生相应的三进制串，并且编程电路用三进制串输入并以相应的对存储的三级细胞。存储装置还可以包括读取电路，读取相应的三电平单元对中的存储的三进制串，以及基于所存储的三进制字符串输入的解码电路，并且基于该代码生成三位的相应串。

4. 发明申请

US20080106937A1 MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MANAGING 有权
标题翻译：使用三级细胞的记忆装置和相关的管理方法
公开(公告)号：US20080106937A1
公开(公告)日：2008-05-08
申请号：US11934144
申请日：2007-11-02
申请人： Alessandro MAGNAVACCA , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
发明人： Alessandro MAGNAVACCA , Massimiliano Scotti , Nicola Del Gatto , Claudio Nava , Marco Ferrario , Massimiliano Mollichelli
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/3427
摘要： A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.
摘要翻译：存储器件可以包括可寻址的三电平单元的阵列，编码电路以三比特串输入，并且基于代码产生相应的三进制串，并且编程电路用三进制串输入并以相应的对存储的三级细胞。存储装置还可以包括读取电路，读取相应的三电平单元对中的存储的三进制串，以及基于所存储的三进制字符串输入的解码电路，并且基于该代码生成三位的相应串。

5. 发明授权

US06940756B2 Non-volatile memory device with improved sequential programming speed 有权
标题翻译：具有改进的顺序编程速度的非易失性存储器件
公开(公告)号：US06940756B2
公开(公告)日：2005-09-06
申请号：US10739928
申请日：2003-12-18
申请人： Francesco Mastroianni , Massimiliano Scotti , Antonio Geraci , Andrea Pozzato
发明人： Francesco Mastroianni , Massimiliano Scotti , Antonio Geraci , Andrea Pozzato
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C2216/14
摘要： A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.
摘要翻译：适用于以顺序模式编程的非易失性存储器件。该装置包括多个存储单元块，每个存储单元块用于存储单词，每个块由地址标识。用于在编程程序开始时加载输入地址的输入电路和用于将内部地址设置为输入地址的内部电路。该装置还包括用于连续加载预定数量的输入字的数据输入电路和用于锁存由预定数量的输入字构成的页的锁存电路。然后，存储器执行编程操作，包括在从内部地址开始的连续地址识别的块中写入页面，并且响应于编程操作的完成来增加预定数量的内部地址。

6. 发明申请

US20060171204A1 Memory device and method for operating the same with high rejection of the noise on the high-voltage supply line 有权
标题翻译：用于高压电源线上高噪声抑制的操作的存储器件和方法
公开(公告)号：US20060171204A1
公开(公告)日：2006-08-03
申请号：US11241729
申请日：2005-09-30
申请人： Nocola Del Gatto , Massimiliano Mollichelli , Massimiliano Scotti , Marco Sforzin
发明人： Nocola Del Gatto , Massimiliano Mollichelli , Massimiliano Scotti , Marco Sforzin
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/30
摘要： A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
摘要翻译：存储器件具有存储器单元阵列。列解码器被配置为寻址存储器单元。电荷泵供应电路为列解码器产生升压的电源电压。连接级布置在电源电路和列解码器之间。连接级在高阻抗状态和低阻抗状态之间切换，并且被配置为在存储器件的给定操作条件下，特别是在读取步骤期间切换到高阻抗状态。

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