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1. 发明授权

US08159044B1 Density transition zones for integrated circuits 有权
标题翻译：集成电路密度过渡区
公开(公告)号：US08159044B1
公开(公告)日：2012-04-17
申请号：US12623161
申请日：2009-11-20
申请人： Shuxian Chen , Fangyun Richter , Bradley Jensen , Yowjuang (Bill) Liu
发明人： Shuxian Chen , Fangyun Richter , Bradley Jensen , Yowjuang (Bill) Liu
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L23/522 , H01L27/0207 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.
摘要翻译：集成电路设置有螺旋电感器和围绕螺旋电感器的过渡区域。过渡区域可以具有基本上八边形或八边形的几何形状。过渡区域中的金属层可以具有基本上八边形并且以行和列排列的金属填充物。如果需要，方形或矩形金属填充物与基本上八角形的金属填充物平铺。金属层也可以包含一半或四分之八角金属填充物。过渡区中的衬底可以具有由浅沟槽隔离区隔开的八边形衬底区域。衬底上方的多晶硅层可以具有直接在衬底中的浅沟槽区域上方的多晶硅的正方形区域。这种布置可以在具有某些几何形状的过渡区域中提供更均匀的密度。

2. 发明授权

US07291546B1 Method and apparatus for reducing charge loss in a nonvolatile memory cell 有权
标题翻译：用于减少非易失性存储单元中的电荷损失的方法和装置
公开(公告)号：US07291546B1
公开(公告)日：2007-11-06
申请号：US10872618
申请日：2004-06-21
申请人： Irfan Rahim , Fangyun Richter
发明人： Irfan Rahim , Fangyun Richter
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/66825
摘要： A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.
摘要翻译：公开了一种在半导体衬底上制造非易失性存储单元的方法。指定用于浮动多晶硅层的半导体衬底的第一区域的区域被封闭，而指定用于非浮动多晶硅层的第二半导体衬底的区域被暴露。半导体衬底的暴露区域掺杂有电荷。

3. 发明授权

US08921217B2 Methods of forming gate structures for reduced leakage 有权
标题翻译：形成栅极结构以减少泄漏的方法
公开(公告)号：US08921217B2
公开(公告)日：2014-12-30
申请号：US13331055
申请日：2011-12-20
申请人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
发明人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： G06F17/5081
摘要： Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
摘要翻译：提供了包含晶体管的集成电路。晶体管可以包括形成在相关联的阱区上的栅极结构。阱区可以被主动偏置并且可以用作身体终端。一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置，则可能产生大量的泄漏。可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域，并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。如果栅极阱对太靠近，则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。

4. 发明授权

US08912104B1 Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization 有权
标题翻译：具有图案化热调节层的集成电路的设计优化方法
公开(公告)号：US08912104B1
公开(公告)日：2014-12-16
申请号：US13047664
申请日：2011-03-14
申请人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
发明人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
IPC分类号： H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/6659 , H01L21/2686 , H01L21/324 , H01L21/823412 , H01L21/823418
摘要： An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
摘要翻译：集成电路可以包括其中形成晶体管的衬底。晶体管可以与电路块相关联。一些电路块可被配置为减少漏电流。可以选择性地加热电路块的选定子集，以通过掺杂剂扩散减小其晶体管的沟道长度，从而加强相对于其它电路块的那些电路块。选择性加热可以通过用图案化的材料层（例如由无定形碳或反射涂层形成的图案化抗反射涂层）涂覆集成电路上的电路块来实现。在应用红外光时，涂层和未涂覆的区域将升高到不同的温度，有选择地加强集成电路上所需的电路块。

5. 发明授权

US07285454B1 Bipolar transistors with low base resistance for CMOS integrated circuits 有权
标题翻译：用于CMOS集成电路的具有低基极电阻的双极晶体管
公开(公告)号：US07285454B1
公开(公告)日：2007-10-23
申请号：US11207461
申请日：2005-08-19
申请人： Minchang Liang , Yow-Juang Liu , Fangyun Richter
发明人： Minchang Liang , Yow-Juang Liu , Fangyun Richter
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/735
摘要： Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.
摘要翻译：提供了具有双极晶体管的互补金属氧化物半导体（CMOS）集成电路及其制造方法。双极晶体管可以具有轻掺杂的基极区域。为了减小与轻掺杂基极区域的电接触相关联的电阻，可以提供进入基极区域的低电阻电流通路。低电阻电流路径可以由由重掺杂外延晶体半导体形成的基极导体提供。具有窄栅极的金属氧化物半导体（MOS）晶体管可以形成在与双极晶体管相同的衬底上。可以使用自对准工艺来形成MOS栅极，其中图案化的栅极导体层用作注入掩模和栅极导体。可以将与图案化的栅极导体层分离的基底掩模层用作用于限定轻掺杂基极区域的注入掩模。

6. 发明授权

US06972466B1 Bipolar transistors with low base resistance for CMOS integrated circuits 失效
标题翻译：用于CMOS集成电路的具有低基极电阻的双极晶体管
公开(公告)号：US06972466B1
公开(公告)日：2005-12-06
申请号：US10784417
申请日：2004-02-23
申请人： Minchang Liang , Yow-Juang Liu , Fangyun Richter
发明人： Minchang Liang , Yow-Juang Liu , Fangyun Richter
IPC分类号： H01L21/84 , H01L27/12 , H01L29/735 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/735
摘要： Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.
摘要翻译：提供了具有双极晶体管的互补金属氧化物半导体（CMOS）集成电路及其制造方法。双极晶体管可以具有轻掺杂的基极区域。为了减小与轻掺杂基极区域的电接触相关联的电阻，可以提供进入基极区域的低电阻电流通路。低电阻电流路径可以由由重掺杂外延晶体半导体形成的基极导体提供。具有窄栅极的金属氧化物半导体（MOS）晶体管可以形成在与双极晶体管相同的衬底上。可以使用自对准工艺来形成MOS栅极，其中图案化的栅极导体层用作注入掩模和栅极导体。可以将与图案化的栅极导体层分离的基底掩模层用作用于限定轻掺杂基极区域的注入掩模。

7. 发明授权

US08835265B1 High-k dielectric device and process 有权
标题翻译：高k电介质器件及工艺
公开(公告)号：US08835265B1
公开(公告)日：2014-09-16
申请号：US13525864
申请日：2012-06-18
申请人： Che Ta Hsu , Fangyun Richter , Ning Cheng , Jeffrey Xiaoqi Tung
发明人： Che Ta Hsu , Fangyun Richter , Ning Cheng , Jeffrey Xiaoqi Tung
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8232 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7833 , H01L21/02115 , H01L21/02126 , H01L21/0217 , H01L21/31111 , H01L21/8232 , H01L21/8238 , H01L21/823857 , H01L27/092 , H01L29/401 , H01L29/4958 , H01L29/517 , H01L29/66477 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.
摘要翻译：绝缘层形成在半导体衬底上; 并且在要形成晶体管栅极的绝缘层中构图孔。在绝缘层的上表面和孔上形成硬掩模间隔层。接下来，间隔层被各向异性蚀刻以去除在每个孔的底部暴露的间隔层的部分以及绝缘层的上表面上的间隔层的部分。然而，蚀刻工艺不会去除在孔的基本上垂直的侧壁上形成的间隔层的所有部分。然后在间隔层的剩余垂直部分和暴露的基板和绝缘层的上表面上形成高k电介质层。然后在高k电介质层上形成金属层; 并完成各个门结构。

8. 发明授权

US08765541B1 Integrated circuit and a method to optimize strain inducing composites 有权
标题翻译：集成电路和优化应变诱导复合材料的方法
公开(公告)号：US08765541B1
公开(公告)日：2014-07-01
申请号：US13214056
申请日：2011-08-19
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/165 , H01L29/267
摘要： A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.
摘要翻译：公开了一种设计IC的方法，以提供应变诱导复合材料的均匀沉积。设计IC的方法包括：确定IC设计上的总应变诱导沉积区域。然后，将总应变诱导沉积区域与预定尺寸进行比较。当总应变诱导沉积面积低于预定尺寸时，修改虚拟扩散区域以增加总应变诱导沉积面积。最后，应变诱导沉积区域被优化。还公开了制造IC和IC的方法。

9. 发明授权

US08664725B1 Strain enhanced transistors with adjustable layouts 有权
标题翻译：具有可调布局的应变增强型晶体管
公开(公告)号：US08664725B1
公开(公告)日：2014-03-04
申请号：US13040538
申请日：2011-03-04
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/1054 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L27/3223 , H01L29/0692 , H01L29/41758 , H01L29/4238 , H01L29/66545 , H01L29/6681 , H01L29/76 , H01L29/7848 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.
摘要翻译：晶体管可以包括诸如矩形掺杂硅阱的半导体区域。栅极指可能与硅阱重叠。栅极指状物可以由多晶硅形成，并且可以沿着阱的长度彼此间隔开固定的栅极 - 栅极间隔。阱的边缘可以被场氧化物包围。可以在井中形成外延区域，以在位于栅极指的下方的沟道区域中产生压缩或拉伸应力。外延区可以形成源极 - 漏极端子。场氧化物的边缘可以与最近的栅极指边缘分开距离，该距离由计算机辅助设计工具自动调整并且可能大于栅极到栅极间距。可以提供虚拟门指结构以确保产生所需的应力水平。

10. 发明申请

US20130157451A1 METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE 有权
标题翻译：形成用于减少泄漏的门结构的方法
公开(公告)号：US20130157451A1
公开(公告)日：2013-06-20
申请号：US13331055
申请日：2011-12-20
申请人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
发明人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
IPC分类号： H01L21/3205 , G06F17/50
CPC分类号： G06F17/5081
摘要： Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
摘要翻译：提供了包含晶体管的集成电路。晶体管可以包括形成在相关联的阱区上的栅极结构。阱区可以被主动偏置并且可以用作身体终端。一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置，则可能产生大量的泄漏。可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域，并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。如果栅极阱对太靠近，则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。

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