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1. 发明授权

US08912104B1 Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization 有权
标题翻译：具有图案化热调节层的集成电路的设计优化方法
公开(公告)号：US08912104B1
公开(公告)日：2014-12-16
申请号：US13047664
申请日：2011-03-14
申请人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
发明人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
IPC分类号： H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/6659 , H01L21/2686 , H01L21/324 , H01L21/823412 , H01L21/823418
摘要： An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
摘要翻译：集成电路可以包括其中形成晶体管的衬底。晶体管可以与电路块相关联。一些电路块可被配置为减少漏电流。可以选择性地加热电路块的选定子集，以通过掺杂剂扩散减小其晶体管的沟道长度，从而加强相对于其它电路块的那些电路块。选择性加热可以通过用图案化的材料层（例如由无定形碳或反射涂层形成的图案化抗反射涂层）涂覆集成电路上的电路块来实现。在应用红外光时，涂层和未涂覆的区域将升高到不同的温度，有选择地加强集成电路上所需的电路块。

2. 发明授权

US08921217B2 Methods of forming gate structures for reduced leakage 有权
标题翻译：形成栅极结构以减少泄漏的方法
公开(公告)号：US08921217B2
公开(公告)日：2014-12-30
申请号：US13331055
申请日：2011-12-20
申请人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
发明人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： G06F17/5081
摘要： Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
摘要翻译：提供了包含晶体管的集成电路。晶体管可以包括形成在相关联的阱区上的栅极结构。阱区可以被主动偏置并且可以用作身体终端。一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置，则可能产生大量的泄漏。可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域，并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。如果栅极阱对太靠近，则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。

3. 发明授权

US08835265B1 High-k dielectric device and process 有权
标题翻译：高k电介质器件及工艺
公开(公告)号：US08835265B1
公开(公告)日：2014-09-16
申请号：US13525864
申请日：2012-06-18
申请人： Che Ta Hsu , Fangyun Richter , Ning Cheng , Jeffrey Xiaoqi Tung
发明人： Che Ta Hsu , Fangyun Richter , Ning Cheng , Jeffrey Xiaoqi Tung
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8232 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7833 , H01L21/02115 , H01L21/02126 , H01L21/0217 , H01L21/31111 , H01L21/8232 , H01L21/8238 , H01L21/823857 , H01L27/092 , H01L29/401 , H01L29/4958 , H01L29/517 , H01L29/66477 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.
摘要翻译：绝缘层形成在半导体衬底上; 并且在要形成晶体管栅极的绝缘层中构图孔。在绝缘层的上表面和孔上形成硬掩模间隔层。接下来，间隔层被各向异性蚀刻以去除在每个孔的底部暴露的间隔层的部分以及绝缘层的上表面上的间隔层的部分。然而，蚀刻工艺不会去除在孔的基本上垂直的侧壁上形成的间隔层的所有部分。然后在间隔层的剩余垂直部分和暴露的基板和绝缘层的上表面上形成高k电介质层。然后在高k电介质层上形成金属层; 并完成各个门结构。

4. 发明授权

US08765541B1 Integrated circuit and a method to optimize strain inducing composites 有权
标题翻译：集成电路和优化应变诱导复合材料的方法
公开(公告)号：US08765541B1
公开(公告)日：2014-07-01
申请号：US13214056
申请日：2011-08-19
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/165 , H01L29/267
摘要： A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.
摘要翻译：公开了一种设计IC的方法，以提供应变诱导复合材料的均匀沉积。设计IC的方法包括：确定IC设计上的总应变诱导沉积区域。然后，将总应变诱导沉积区域与预定尺寸进行比较。当总应变诱导沉积面积低于预定尺寸时，修改虚拟扩散区域以增加总应变诱导沉积面积。最后，应变诱导沉积区域被优化。还公开了制造IC和IC的方法。

5. 发明授权

US08664725B1 Strain enhanced transistors with adjustable layouts 有权
标题翻译：具有可调布局的应变增强型晶体管
公开(公告)号：US08664725B1
公开(公告)日：2014-03-04
申请号：US13040538
申请日：2011-03-04
申请人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
发明人： Girish Venkitachalam , Che Ta Hsu , Fangyun Richter , Peter J. McElheny
IPC分类号： H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/1054 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L27/3223 , H01L29/0692 , H01L29/41758 , H01L29/4238 , H01L29/66545 , H01L29/6681 , H01L29/76 , H01L29/7848 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.
摘要翻译：晶体管可以包括诸如矩形掺杂硅阱的半导体区域。栅极指可能与硅阱重叠。栅极指状物可以由多晶硅形成，并且可以沿着阱的长度彼此间隔开固定的栅极 - 栅极间隔。阱的边缘可以被场氧化物包围。可以在井中形成外延区域，以在位于栅极指的下方的沟道区域中产生压缩或拉伸应力。外延区可以形成源极 - 漏极端子。场氧化物的边缘可以与最近的栅极指边缘分开距离，该距离由计算机辅助设计工具自动调整并且可能大于栅极到栅极间距。可以提供虚拟门指结构以确保产生所需的应力水平。

6. 发明申请

US20130157451A1 METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE 有权
标题翻译：形成用于减少泄漏的门结构的方法
公开(公告)号：US20130157451A1
公开(公告)日：2013-06-20
申请号：US13331055
申请日：2011-12-20
申请人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
发明人： Wuu-Cherng Lin , Fangyun Richter , Che Ta Hsu , Wen Sun Wu
IPC分类号： H01L21/3205 , G06F17/50
CPC分类号： G06F17/5081
摘要： Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
摘要翻译：提供了包含晶体管的集成电路。晶体管可以包括形成在相关联的阱区上的栅极结构。阱区可以被主动偏置并且可以用作身体终端。一个晶体管的阱区可以邻近相邻晶体管的栅极结构形成。如果相邻晶体管的栅极结构和一个晶体管的阱区都被主动偏置并且彼此靠近放置，则可能产生大量的泄漏。可以使用计算机辅助设计工具来识别主动驱动的栅极端子和阱区域，并且可以用于确定每个栅极 - 阱对是否彼此间隔得足够远。如果栅极阱对太靠近，则设计工具可以定位现有的栅极切割层并延伸现有的栅极切割层以切割主动驱动的栅极结构。

7. 发明授权

US08519403B1 Angled implantation for deep submicron device optimization 失效
标题翻译：用于深亚微米器件优化的角度植入
公开(公告)号：US08519403B1
公开(公告)日：2013-08-27
申请号：US12931584
申请日：2011-02-04
申请人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
发明人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： H01L21/823807 , H01L21/26586 , H01L29/1083
摘要： A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
摘要翻译：一种形成亚微米器件的方法包括在包括第一掺杂剂型的多晶硅阱和第二掺杂剂型的栅极的第一区域和包括第二掺杂剂型多晶硅阱的第二区域的第一区域上沉积硬掩模，第一掺杂剂类型的栅极。第一个区域上的硬掩模被去除。执行第一掺杂剂类型的倾斜植入以在第二掺杂剂类型的栅极下形成凹穴。

8. 发明授权

US07883946B1 Angled implantation for deep submicron device optimization 有权
标题翻译：用于深亚微米器件优化的角度植入
公开(公告)号：US07883946B1
公开(公告)日：2011-02-08
申请号：US12151646
申请日：2008-05-08
申请人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
发明人： Che Ta Hsu , Christopher J. Pass , Dale Ibbotson , Jeffrey T. Watt , Yanzhong Xu
IPC分类号： H01L21/84 , H01L21/22 , H01L21/38
CPC分类号： H01L21/823807 , H01L21/26586 , H01L29/1083
摘要： A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
摘要翻译：一种形成亚微米器件的方法包括在包括第一掺杂剂型的多晶硅阱和第二掺杂剂型的栅极的第一区域和包括第二掺杂剂型多晶硅阱的第二区域的第一区域上沉积硬掩模，第一掺杂剂类型的栅极。第一个区域上的硬掩模被去除。执行第一掺杂剂类型的倾斜植入以在第二掺杂剂类型的栅极下形成凹穴。

9. 发明授权

US08057964B2 Photolithographic reticles with electrostatic discharge protection structures 有权
标题翻译：具有静电放电保护结构的光刻掩模版
公开(公告)号：US08057964B2
公开(公告)日：2011-11-15
申请号：US12263413
申请日：2008-10-31
申请人： Che Ta Hsu , Peter J. McElheny , Jeffrey T. Watt
发明人： Che Ta Hsu , Peter J. McElheny , Jeffrey T. Watt
IPC分类号： G03F1/00 , H01L23/62
CPC分类号： G03F1/40
摘要： Photolithographic reticles are provided that have electrostatic discharge protection features. A photolithographic reticle may be formed from metal structures such as chrome structures on a transparent substrate such as fused silica. Some of the metal structures on the reticle correspond to transistors and other electronic devices on integrated circuits that are fabricated when using the reticles in a step-and-repeat lithography tool. These metal device structures may be susceptible to damage due to electrostatic charge build up during handling of the reticle. To prevent damage, dummy ring structures are formed in the vicinity of device structures. The dummy ring structures may be constructed to be more sensitive to electrostatic discharge than the device structures, so that in the event of an electrostatic discharge, damage is confined to portions of the reticle that are not critical.
摘要翻译：提供具有静电放电保护特征的光刻掩模版。光刻掩模版可以由诸如熔融二氧化硅的透明基板上的诸如铬结构的金属结构形成。掩模版上的一些金属结构对应于在步进重复光刻工具中使用掩模版时制造的集成电路上的晶体管和其他电子器件。这些金属器件结构可能由于在掩模版的处理过程中由于静电电荷的积累而易于损坏。为了防止损坏，在设备结构附近形成虚拟环结构。伪环结构可以被构造成比器件结构对静电放电更敏感，使得在静电放电的情况下，损坏被限制在不太关键的掩模版的部分上。

10. 发明授权

US08056025B1 Integration of open space/dummy metal at CAD for physical debug of new silicon 有权
标题翻译：在CAD中集成开放空间/虚拟金属，用于新型硅的物理调试
公开(公告)号：US08056025B1
公开(公告)日：2011-11-08
申请号：US12035403
申请日：2008-02-21
申请人： Vijay Chowdhury , Che Ta Hsu , Ada Yu
发明人： Vijay Chowdhury , Che Ta Hsu , Ada Yu
IPC分类号： G06F17/50 , G06F19/00 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/2848 , G01R31/2884 , G06F2217/14
摘要： An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.
摘要翻译：访问板用于提供对集成电路（IC）设备的功能块的访问。存取焊盘使用在金属化水平的开放空间中的伪金属形成，该金属化水平位于顶部金属化水平和在IC器件中形成功能块的基极电平之间。在金属化级别的接入焊盘提供接触以访问功能块的底层电路，使得可以在探测期间验证IC器件的功能块的功能完整性。

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