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1. 发明申请

US20110186949A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110186949A1
公开(公告)日：2011-08-04
申请号：US13084996
申请日：2011-04-12
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO , Takaaki KOEN , Yuto YAKUBO , Makoto YANAGISAWA , Hisashi OHTANI , Eiji SUGIYAMA , Nozomi HORIKOSHI
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO , Takaaki KOEN , Yuto YAKUBO , Makoto YANAGISAWA , Hisashi OHTANI , Eiji SUGIYAMA , Nozomi HORIKOSHI
IPC分类号： H01L29/66
CPC分类号： G06K19/07735 , G06K19/07722 , G06K19/07794 , H01L23/295 , H01L23/3157 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.
摘要翻译：一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。其中一个结构体设置在片上天线和增强天线之间。在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

2. 发明申请

US20120112191A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120112191A1
公开(公告)日：2012-05-10
申请号：US13270455
申请日：2011-10-11
申请人： Kiyoshi KATO , Yutaka SHIONOIRI , Shuhei NAGATSUKA , Yuto YAKUBO , Jun KOYAMA
发明人： Kiyoshi KATO , Yutaka SHIONOIRI , Shuhei NAGATSUKA , Yuto YAKUBO , Jun KOYAMA
IPC分类号： H01L29/16
CPC分类号： H01L27/1156 , G11C11/403 , G11C16/0433 , H01L21/84 , H01L27/1203 , H01L27/1225 , H01L28/40
摘要： A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.
摘要翻译：半导体器件或半导体存储器件中的数据保持期延长。半导体器件或半导体存储器包括存储电路，该存储器电路包括第一晶体管，其包括第一半导体层和第一栅极，第二晶体管包括第二半导体层，第二栅极和第三栅极。第一半导体层形成在与包括第二门的层相同。

3. 发明申请

US20110122670A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110122670A1
公开(公告)日：2011-05-26
申请号：US12947846
申请日：2010-11-17
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , G11C5/06 , G11C5/147 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C11/24 , G11C11/4097 , G11C16/0433 , G11C16/28 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L23/528 , H01L27/0688 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/11551 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L29/22 , H01L29/24 , H01L29/26 , H01L29/78 , H01L29/78603 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.
摘要翻译：本发明的目的是提供一种半导体器件，其组合晶体管，其集成在其沟道形成区域中包括氧化物半导体的相同衬底晶体管和在其沟道形成区域中包括非氧化物半导体的晶体管。本发明的应用是实现基本上不需要特定擦除操作的非易失性半导体存储器，并且不会因重复的写入操作而遭受损坏。此外，半导体器件很适合于存储多值数据。在说明书中详细说明制造方法，应用电路和驱动/读取方法。

4. 发明申请

US20090180326A1 Non-Volatile Memory and Semiconductor Device 有权
标题翻译：非易失性存储器和半导体器件
公开(公告)号：US20090180326A1
公开(公告)日：2009-07-16
申请号：US12407539
申请日：2009-03-19
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： G11C16/06
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32
摘要： There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.
摘要翻译：提供了一种在写入操作中实现高精度阈值控制的非易失性存储器。在本发明中，控制存储晶体管的漏极电压和漏极电流，进行热电子注入系统的写入动作，其中电荷注入速度不依赖于阈值电压。图图1A和1B是用于控制写入的电路结构的视图。在图如图1A和1B所示，运算放大器103的输出连接到存储晶体管101的控制栅极，恒流源102连接到漏电极，源电极接地。恒流源102和电压Vpgm分别连接到运算放大器103的两个输入端。

5. 发明申请

US20110101334A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110101334A1
公开(公告)日：2011-05-05
申请号：US12912190
申请日：2010-10-26
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： H01L27/108
CPC分类号： H01L27/088 , G11C11/404 , G11C11/405 , G11C16/02 , H01L27/0207 , H01L27/1052 , H01L27/115 , H01L27/11517 , H01L27/1156 , H01L27/1225
摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.
摘要翻译：本发明的目的是提供具有新颖结构的半导体。在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

6. 发明申请

US20100253478A1 DATA PROCESSING DEVICE, IC CARD AND COMMUNICATION SYSTEM 有权
标题翻译：数据处理设备，IC卡和通信系统
公开(公告)号：US20100253478A1
公开(公告)日：2010-10-07
申请号：US12754416
申请日：2010-04-05
申请人： Jun KOYAMA , Kiyoshi KATO , Shunpei YAMAZAKI
发明人： Jun KOYAMA , Kiyoshi KATO , Shunpei YAMAZAKI
IPC分类号： H04Q5/22
CPC分类号： H04W52/028 , Y02D70/122 , Y02D70/166
摘要： An object is to provide a data processing device which achieves multiple functions or easy additional providing of a function while suppressing adverse influence on a communication distance or to improve resistance to electrostatic discharge in the data processing device. The data processing device includes an antenna which transmits and receives a first signal to/from a first terminal device through wireless communication, an integrated circuit which executes a process in accordance with the first signal, and a terminal portion which transmits and receives a second signal to/from a second terminal device and has an exposed conductive portion on its surface. A protection circuit is provided between at least one terminal of terminals of the terminal portion and a power supply terminal of a high potential and between the one terminal and a power supply terminal of a low potential.
摘要翻译：本发明的目的是提供一种能够实现多种功能的数据处理装置，或容易地附加提供功能，同时抑制对通信距离的不利影响或提高数据处理装置中的静电放电的抵抗力。数据处理装置包括通过无线通信向第一终端装置发送第一信号的接收天线，执行与第一信号对应的处理的集成电路以及发送接收第二信号的终端部到/从第二终端设备，并且在其表面上具有暴露的导电部分。在端子部分的端子的至少一个端子和高电位的电源端子之间以及在一个端子和低电位的电源端子之间提供保护电路。

7. 发明申请

US20110297928A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110297928A1
公开(公告)日：2011-12-08
申请号：US13117588
申请日：2011-05-27
申请人： Atsuo ISOBE , Yoshinori IEDA , Keitaro IMAI , Kiyoshi KATO , Yuto YAKUBO , Yuki HATA
发明人： Atsuo ISOBE , Yoshinori IEDA , Keitaro IMAI , Kiyoshi KATO , Yuto YAKUBO , Yuki HATA
IPC分类号： H01L27/105
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/1156 , H01L27/1225 , H01L28/60
摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.
摘要翻译：提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。因此，可以提高半导体器件的集成度。

8. 发明申请

US20110241008A1 SEMICONDUCTOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体显示装置及其制造方法
公开(公告)号：US20110241008A1
公开(公告)日：2011-10-06
申请号：US13162791
申请日：2011-06-17
申请人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Masahiko HAYAKAWA , Kiyoshi KATO , Mitsuaki OSAME , Takashi HIROSUE , Saishi FUJIKAWA
发明人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Masahiko HAYAKAWA , Kiyoshi KATO , Mitsuaki OSAME , Takashi HIROSUE , Saishi FUJIKAWA
IPC分类号： H01L33/08
CPC分类号： H01L27/1244 , G02F1/136204 , H01L21/76804 , H01L21/76831 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L29/78645 , H01L51/0037 , Y10S257/906 , Y10S257/908
摘要： A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is foamed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.
摘要翻译：具有层间绝缘膜的半导体显示装置，其中以有限的成膜时间确保表面水平度，用于除去水分的热处理不需要很长时间，并且防止层间绝缘膜中的水分逸出到邻近的膜或电极层间绝缘膜。形成TFT，然后形成与有机树脂膜相比传递较少水分的含氮无机绝缘膜，以覆盖TFT。接下来，施加包含感光性丙烯酸树脂的有机树脂，并通过将有机树脂膜部分地曝光而形成开口。然后将开口发泡的有机树脂膜用含有无机绝缘膜覆盖，所述无机绝缘膜比有机树脂膜透湿少。此后，在有机树脂膜的开口部分将栅极绝缘膜和含氮无机绝缘膜的两层部分地蚀刻掉，以暴露TFT的有源层。

9. 发明申请

US20120074481A1 SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：证券，芯片安装产品及其制造方法
公开(公告)号：US20120074481A1
公开(公告)日：2012-03-29
申请号：US13314280
申请日：2011-12-08
申请人： Shunpei YAMAZAKI , Kiyoshi KATO
发明人： Shunpei YAMAZAKI , Kiyoshi KATO
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L23/49855 , G06K19/07749 , G06K19/07758 , G06K19/07767 , G07D7/01 , H01L2924/0002 , H01L2924/00
摘要： The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.
摘要翻译：本发明提供一种具有降低成本，增加耐冲击性和有吸引力的设计的ID芯片以及安装ID芯片的产品等及其制造方法。鉴于上述，将厚度为0.2μm以下的半导体膜的集成电路安装在包括纸币，财物，食品和饮料容器等的证券（以下称为产品等）上。与保持有吸引力的设计的硅晶片上形成的芯片相比，本发明的ID芯片可以降低成本并增加耐冲击性。

10. 发明申请

US20110049522A1 SEMICONDUCTOR DISPLAY DEVICE 有权
标题翻译：半导体显示设备
公开(公告)号：US20110049522A1
公开(公告)日：2011-03-03
申请号：US12711611
申请日：2010-02-24
申请人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Masahiko HAYAKAWA , Kiyoshi KATO , Mitsuaki OSAME
发明人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Masahiko HAYAKAWA , Kiyoshi KATO , Mitsuaki OSAME
IPC分类号： H01L33/00
CPC分类号： H01L27/1248 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L27/1244 , H01L27/1255 , H01L27/13 , H01L27/3246 , H01L27/3276 , H01L33/52 , H01L51/5237 , H01L51/5253
摘要： It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially is by etching to expose an active layer of the TFT.
摘要翻译：本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。然后，在有机树脂膜的开口部分，通过蚀刻部分地开启含有氮的栅极绝缘膜和双层无机绝缘膜，以暴露TFT的有源层。

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