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    • 9. 发明申请
    • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20080142921A1
    • 2008-06-19
    • US11955496
    • 2007-12-13
    • Atsuo ISOBESuguru OZAWA
    • Atsuo ISOBESuguru OZAWA
    • H01L27/12H01L21/22
    • H01L27/1266H01L27/124H01L29/458
    • To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening. Since the second impurity element is added through the second opening, the periphery of the second opening is also doped with a slight amount of the second impurity element. Therefore, the first impurity region and the second wiring are located away a short distance from each other such that they are not shorted.
    • 为了制造由于寄生电阻引起的导通电流的降低被抑制的肖特基势垒二极管,抑制了导通电流的变化,抑制了关断电流的增大。 该制造方法包括形成岛状半导体膜的步骤; 用第一杂质元素掺杂岛状半导体膜以形成第一杂质区; 形成绝缘膜以覆盖岛状半导体膜; 蚀刻绝缘膜以形成部分地暴露第一杂质区的第一开口和第二开口; 在所述绝缘膜上形成掩模以覆盖所述第一开口并暴露所述第二开口; 用第二杂质元素掺杂第一杂质区以形成第二杂质区; 以及形成与在所述第一开口处暴露的所述第一杂质区域接触的第一布线,以及形成与在所述第二开口处露出的所述第二杂质区域接触的第二布线。 由于通过第二开口添加第二杂质元素,所以第二开口的周边也掺杂有少量的第二杂质元素。 因此,第一杂质区域和第二布线彼此距离很短,使得它们不短路。