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1. 发明申请

US20110193080A1 Semiconductor device and electronic appliance 有权
标题翻译：半导体器件和电子设备
公开(公告)号：US20110193080A1
公开(公告)日：2011-08-11
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

2. 发明申请

US20110180796A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110180796A1
公开(公告)日：2011-07-28
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/24
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

3. 发明申请

US20100283105A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283105A1
公开(公告)日：2010-11-11
申请号：US12840442
申请日：2010-07-21
申请人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译：提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。导电层在形成于半导体层的开口的侧面与半导体层电连接。

4. 发明申请

US20080237875A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080237875A1
公开(公告)日：2008-10-02
申请号：US12046817
申请日：2008-03-12
申请人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L23/52 , H01L21/28
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译：提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。导电层在形成于半导体层的开口的侧面与半导体层电连接。

5. 发明申请

US20110287605A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20110287605A1
公开(公告)日：2011-11-24
申请号：US13198171
申请日：2011-08-04
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.
摘要翻译：在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层，通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层，所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理，具有激光的晶体半导体层。

6. 发明申请

US20090239354A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20090239354A1
公开(公告)日：2009-09-24
申请号：US12399047
申请日：2009-03-06
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.
摘要翻译：在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层，通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层，所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理，具有激光的晶体半导体层。

7. 发明申请

US20110210326A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110210326A1
公开(公告)日：2011-09-01
申请号：US13029146
申请日：2011-02-17
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , G11C16/0408 , G11C16/0483 , H01L27/11521 , H01L27/1156 , H01L29/41733 , H01L29/45 , H01L29/66969
摘要： A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.
摘要翻译：半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极，以及在氧化物半导体层和栅电极之间的栅极绝缘层，源电极或漏电极包括第一导电层和第二导电层，第二导电层具有在沟道长度方向上延伸超出第一导电层的端部并且与栅电极的一部分重叠的区域，其中侧壁绝缘层设置在第二导电层的延伸区域上，并且其中侧壁绝缘层包括多个不同材料层的堆叠。

8. 发明申请

US20120074407A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120074407A1
公开(公告)日：2012-03-29
申请号：US13021343
申请日：2011-02-04
申请人： Shunpei YAMAZAKI , Teruyuki FUJII , Ryota IMAHAYASHI , Shinya SASAGAWA , Motomu KURATA , Fumika TAGUCHI
发明人： Shunpei YAMAZAKI , Teruyuki FUJII , Ryota IMAHAYASHI , Shinya SASAGAWA , Motomu KURATA , Fumika TAGUCHI
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , G11C16/0416 , G11C16/0433 , G11C16/28 , H01L27/1052 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
摘要翻译：目的是提供一种具有新颖结构的半导体器件，其中包括氧化物半导体的晶体管和包括氧化物半导体之外的半导体材料的晶体管被堆叠。该半导体器件包括第一晶体管，第一晶体管上的绝缘层和绝缘层上的第二晶体管。在半导体器件中，第一晶体管包括第一沟道形成区，第二晶体管包括第二沟道形成区，第一沟道形成区包括与第二沟道形成区的半导体材料不同的半导体材料，绝缘层包括均方根表面粗糙度小于或等于1nm的表面。

9. 发明申请

US20120193625A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20120193625A1
公开(公告)日：2012-08-02
申请号：US13357902
申请日：2012-01-25
申请人： Shinya SASAGAWA , Motomu KURATA
发明人： Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66969 , H01L21/441 , H01L29/41733 , H01L29/7869
摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.
摘要翻译：本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

10. 发明申请

US20110147745A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110147745A1
公开(公告)日：2011-06-23
申请号：US12973123
申请日：2010-12-20
申请人： Shinya SASAGAWA , Akihiro ISHIZUKA , Shinobu FURUKAWA , Motomu KURATA
发明人： Shinya SASAGAWA , Akihiro ISHIZUKA , Shinobu FURUKAWA , Motomu KURATA
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.
摘要翻译：一个实施例是一种薄膜晶体管，其包括栅极电极层，设置为覆盖栅极电极层的栅极绝缘层; 与栅电极层完全重叠的第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触，并具有比第一半导体层低的载流子迁移率; 设置成与所述第二半导体层接触的杂质半导体层; 侧壁绝缘层，设置成覆盖所述第一半导体层的至少一个侧壁; 以及与至少所述杂质半导体层接触地设置的源极和漏极电极层。第二半导体层可以由在第一半导体层上彼此分开的部分组成。

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