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1. 发明授权

US09064827B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09064827B2
公开(公告)日：2015-06-23
申请号：US11806720
申请日：2007-06-04
申请人： Teruyuki Fujii
发明人： Teruyuki Fujii
IPC分类号： H01L51/40 , H01L27/32 , H01L29/45 , H01L51/56 , H01L27/12
CPC分类号： H01L27/3246 , H01L27/1248 , H01L27/3283 , H01L29/458 , H01L51/56
摘要： An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. As a method for forming the partition wall, nano-imprinting is used. An insulating layer contains polysilane. The partition wall formed of a silicon oxide film is formed by UV light irradiation and heating.
摘要翻译：目的在于提供以低成本制造的具有优异再现性的半导体器件。一种制造半导体器件的方法包括以下步骤：在衬底上形成第一电极; 在所述基板和所述第一电极上形成绝缘层; 将模具压在绝缘层上以在绝缘层中形成开口; 将模具与形成有开口的绝缘层分离; 硬化其中形成开口的绝缘层以形成分隔壁; 在所述第一电极和所述分隔壁上形成发光层; 以及在所述发光层上形成第二电极。作为形成分隔壁的方法，使用纳米压印。绝缘层含有聚硅烷。由氧化硅膜形成的分隔壁通过UV光照射和加热形成。

2. 发明授权

US08384601B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08384601B2
公开(公告)日：2013-02-26
申请号：US13361988
申请日：2012-01-31
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H01Q1/38
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
摘要翻译：本发明的目的是为了防止在具有集成电路的半导体器件中的电路元件的电气特性受到不利影响，并且在一个衬底上形成天线，该衬底使用用于天线的铜电镀。另一个目的是防止在具有集成电路的半导体器件中的天线与集成电路之间的不良连接导致半导体器件的缺陷，并且形成在一个衬底上的天线。在具有集成电路100和在一个基板102上形成的天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以减少对电路元件的电特性的不利影响，由于天线101的基极层107使用预定金属的氮化物膜而导致铜扩散。

3. 发明申请

US20120146065A1 LIGHTING EMITTING DEVICE, MANUFACTURING METHOD OF THE SAME, ELECTRONIC DEVICE HAVING THE SAME 有权
标题翻译：照明发光装置及其制造方法，具有该发光装置的电子装置
公开(公告)号：US20120146065A1
公开(公告)日：2012-06-14
申请号：US13334150
申请日：2011-12-22
申请人： Teruyuki Fujii , Shunpei Yamazaki
发明人： Teruyuki Fujii , Shunpei Yamazaki
IPC分类号： H01J1/63 , H01L33/62
CPC分类号： H01L27/3251 , G06F1/1637 , G09G3/3225 , G09G2300/08 , G09G2320/0626 , G09G2380/14 , H01L25/0753 , H01L27/156 , H01L27/3246 , H01L27/3267 , H01L31/0232 , H01L33/08 , H01L33/44 , H01L33/502 , H01L33/60 , H01L51/0011 , H01L51/5012 , H01L51/5237 , H01L51/5246 , H01L51/5253 , H01L51/5262 , H01L2251/558 , H01L2924/0002 , Y10T428/24942 , H01L2924/00
摘要： One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.
摘要翻译：一个像素被分成包括第一发光元件的第一区域和包括第二发光元件的第二区域，其中第一区域在一个方向上发光，而第二区域沿与第一区域相反的方向发光。独立地驱动第一发光元件和第二发光元件允许在表面上独立地显示图像。

4. 发明授权

US08053253B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08053253B2
公开(公告)日：2011-11-08
申请号：US12473320
申请日：2009-05-28
申请人： Yuugo Goto , Teruyuki Fujii
发明人： Yuugo Goto , Teruyuki Fujii
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/552 , H01L23/60 , H01L23/66 , H01L2223/6677 , H01L2924/0002 , H01L2924/12044 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.
摘要翻译：目的是提供一种高度可靠的对外部应力和静电放电具有耐受性的半导体器件。另一个目的是防止在制造过程中由于外部应力或静电放电引起的形状不良和缺陷特性，并且以高产率制造半导体器件。另一个目的是以低成本和高生产率制造半导体器件。通过使用覆盖半导体集成电路的导电屏蔽，可以防止由于半导体集成电路的静电放电引起的静电击穿。导电屏蔽形成为使得至少顶表面和底表面上的导电屏蔽通过电镀方法电连接。此外，由于使用电镀方法来形成导电屏蔽，所以可以以低成本高生产率形成半导体器件。

5. 发明授权

US07969363B2 Semiconductor device 有权
公开(公告)号：US07969363B2
公开(公告)日：2011-06-28
申请号：US12830195
申请日：2010-07-02
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H01Q1/38
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.

6. 发明申请

US20090305467A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090305467A1
公开(公告)日：2009-12-10
申请号：US12473320
申请日：2009-05-28
申请人： Yuugo GOTO , Teruyuki FUJII
发明人： Yuugo GOTO , Teruyuki FUJII
IPC分类号： H01L21/58
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/552 , H01L23/60 , H01L23/66 , H01L2223/6677 , H01L2924/0002 , H01L2924/12044 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： An object is to provide a highly reliable semiconductor device that is reduced in thickness and size and has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.
摘要翻译：目的是提供一种可靠性低的半导体器件，其厚度和尺寸减小，并具有对外部应力和静电放电的耐受性。另一个目的是防止在制造过程中由于外部应力或静电放电引起的形状不良和缺陷特性，并且以高产率制造半导体器件。另一个目的是以低成本和高生产率制造半导体器件。通过使用覆盖半导体集成电路的导电屏蔽，可以防止由于半导体集成电路的静电放电引起的静电击穿（电路的故障或半导体元件的损坏）。导电屏蔽形成为使得至少顶表面和底表面上的导电屏蔽通过电镀方法电连接。此外，由于使用电镀方法来形成导电屏蔽，所以可以以低成本高生产率形成半导体器件。

7. 发明授权

US07199520B2 Lighting emitting device and electronic apparatus having the same 有权
标题翻译：照明发光装置及具有该照明装置的电子设备
公开(公告)号：US07199520B2
公开(公告)日：2007-04-03
申请号：US10760716
申请日：2004-01-21
申请人： Teruyuki Fujii , Shunpei Yamazaki
发明人： Teruyuki Fujii , Shunpei Yamazaki
IPC分类号： H01J1/70
CPC分类号： H01L27/3251 , G06F1/1637 , G09G3/3225 , G09G2300/08 , G09G2320/0626 , G09G2380/14 , H01L25/0753 , H01L27/156 , H01L27/3246 , H01L27/3267 , H01L31/0232 , H01L33/08 , H01L33/44 , H01L33/502 , H01L33/60 , H01L51/0011 , H01L51/5012 , H01L51/5237 , H01L51/5246 , H01L51/5253 , H01L51/5262 , H01L2251/558 , H01L2924/0002 , Y10T428/24942 , H01L2924/00
摘要： One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.
摘要翻译：一个像素被分成包括第一发光元件的第一区域和包括第二发光元件的第二区域，其中第一区域在一个方向上发光，而第二区域沿与第一区域相反的方向发光。独立地驱动第一发光元件和第二发光元件允许在表面上独立地显示图像。

8. 发明授权

US09112067B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09112067B2
公开(公告)日：2015-08-18
申请号：US12766389
申请日：2010-04-23
申请人： Teruyuki Fujii , Kohei Ohshima , Junya Maruyama , Akihisa Shimomura
发明人： Teruyuki Fujii , Kohei Ohshima , Junya Maruyama , Akihisa Shimomura
IPC分类号： H01L31/0224 , H01L31/0296 , H01L31/02 , H01L31/028 , H01L31/068 , H01L31/075
CPC分类号： H01L31/022425 , H01L31/02008 , H01L31/028 , H01L31/0296 , H01L31/068 , H01L31/075 , Y02E10/50
摘要： An object relates to an electrode of a semiconductor device or a method for manufacturing a semiconductor device, which includes a bonding step, and problems are: (1) high resistance of a semiconductor device due to the use of an Al electrode, (2) formation of an alloy by Al and Si, (3) high resistance of a film formed by a sputtering method, and (4) defective bonding in a bonding step which is caused if a bonding surface has a large unevenness. A semiconductor device includes a metal substrate or a substrate provided with a metal film, a copper (Cu) plating film over and bonded to the metal substrate or the metal film by employing a thermocompression bonding method, a barrier film over the Cu plating film, a single crystal silicon film over the barrier film, and an electrode layer over the single crystal silicon film.
摘要翻译：本发明涉及一种半导体器件的电极或半导体器件的制造方法，其包括接合工序，其问题是：（1）由于使用Al电极而导致的半导体器件的高电阻，（2）通过Al和Si形成合金，（3）通过溅射法形成的膜的高电阻，以及（4）如果接合表面具有大的不平坦度时引起的接合步骤中的不良接合。半导体装置包括金属基板或具有金属膜的金属基板，通过使用热压接法在金属基板或金属膜上结合的铜（Cu）电镀膜，在Cu镀膜上的阻挡膜，阻挡膜上的单晶硅膜，以及单晶硅膜上的电极层。

9. 发明授权

US07750852B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07750852B2
公开(公告)日：2010-07-06
申请号：US12055918
申请日：2008-03-26
申请人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
发明人： Kazuya Hanaoka , Hideto Ohnuma , Teruyuki Fujii
IPC分类号： H01Q1/38
CPC分类号： H01Q1/2208 , H01Q9/0407 , H01Q23/00
摘要： An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.
摘要翻译：本发明的目的是为了防止电路元件的电特性在具有集成电路的半导体器件和形成在同一衬底上的天线的铜扩散的不利影响，该天线使用用于天线的铜电镀。另一个目的是防止由于在具有集成电路的半导体器件中的天线和集成电路之间的连接不良而导致半导体器件的缺陷，并且天线形成在同一衬底上。在具有形成在一个基板102上的集成电路100和天线101的半导体器件中，当将铜镀层108用于天线101的导体时，可以防止铜扩散到电路元件并降低不利影响由于铜扩散而导致的电路元件的电特性，因为天线101的基极层107使用预定金属的氮化物膜。此外，通过使用氮化镍作为天线的基底层的金属氮化物，可以降低天线与集成电路之间的不良连接。

10. 发明申请

US20090246953A1 Method for Manufacturing Semiconductor Device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20090246953A1
公开(公告)日：2009-10-01
申请号：US12477303
申请日：2009-06-03
申请人： Satoru Okamoto , Teruyuki Fujii , Hideto Ohnuma , Akihiro Ishizuka
发明人： Satoru Okamoto , Teruyuki Fujii , Hideto Ohnuma , Akihiro Ishizuka
IPC分类号： H01L21/3205 , H01L21/3065 , H01L21/306 , H01L21/308
CPC分类号： H01L27/124 , C23F1/20 , C23F1/26 , G02F1/136227 , G02F2001/13629 , H01L21/32134 , H01L21/32136 , H01L21/76838 , H01L21/76885
摘要： It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.
摘要翻译：本发明的目的是提供一种包括具有优选形状的布线的半导体器件。一种制造方法包括以下步骤：形成连接到元件的第一导电层和其上的第二导电层; 在所述第二导电层上形成抗蚀剂掩模; 通过使用掩模的干法蚀刻处理第二导电层; 以及通过左蚀刻法进行湿式蚀刻来处理第一导电层，其中在干蚀刻中第二导电层的蚀刻速率高于第一导电层的蚀刻速率，并且其中第二导电层的蚀刻速率相同等于或大于湿蚀刻中第一导电层的厚度。

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